US5570040A
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Programmable logic array integrated circuit incorporating a first-in first-out memory
Assignee: Altera Corp
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Filing: 1995-03-22
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Granted: 1996-10-29
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Expires: 2015-03-22
Abstract
Abstract A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.
Inventors
- 👤 Craig S. Lytle
- 👤 Donald F. Faria
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:41
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; G; G11; G11C; G11C19/00; H03K19/17704
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
83 words
A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; and a first-in, first-out memory block, programmably coupled to said first plurality of conductors.
Claim 2
Dependent Claim
83 words
A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; and a first-in, first-out memory block, programmably coupled to said first plurality of conductors.
Claim 3
Dependent Claim
28 words
The programmable logic device integrated circuit of claims 1 further comprising: a global clock, coupled to said plurality of logic array blocks and said first-in, first-out memory block.
Claim 4
Dependent Claim
34 words
The programmable logic device integrated circuit of claim 2 further comprising: a first memory clock, coupled to said first-in, first-out memory block; and a second memory clock, coupled to said first-in, first-out memory block.
Claim 5
Dependent Claim
44 words
The programmable logic device integrated circuit of claim 1 wherein said first-in, first-out memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs control operations of said first-in, first-out memory block.
Claim 6
Dependent Claim
46 words
The programmable logic device integrated circuit of claim 1 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said first-in, first-out memory block.
Claim 7
Dependent Claim
44 words
The programmable logic device integrated circuit of claim 1 wherein said first-in, first-out memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicate a status of said first-in, first-out memory block.
Claim 8
Dependent Claim
40 words
The programmable logic device integrated circuit of claim 1 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to said first-in, first-out memory block, without passing through said second plurality of conductors.
Claim 9
Dependent Claim
31 words
The programmable logic device integrated circuit of claim 1 wherein said second plurality of conductors is programmably coupled to said first-in, first-out memory block through a plurality of fully populated multiplexers.
Claim 10
Dependent Claim
31 words
The programmable logic device integrated circuit of claim 1 wherein said second plurality of conductors is programmably coupled to said first-in, first-out memory block through a plurality of partially populated multiplexers.
Claim 11
Dependent Claim
41 words
The programmable logic device integrated circuit of claim 1 further comprising: a crossbar switch, coupled to said first-in, first-out memory block, wherein said second plurality of conductors is programmably coupled through a plurality of partially populated multiplexers to said crossbar switch.
Claim 12
Dependent Claim
43 words
The programmable logic device integrated circuit of claim 1 further comprising: a plurality of input-output blocks, coupled to said plurality of logic array blocks; and an output enable signal, programmably coupled to said plurality of input-output blocks and said first-in, first-out memory block.
Claim 13
Dependent Claim
33 words
A digital processing system comprising: processing unit; memory, coupled to said processing unit; and a programmable logic device integrated circuit as recited in claim 1, coupled to said processing unit and said memory.
Claim 14
Dependent Claim
153 words
A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; and a first-in, first-out memory block, programmably coupled to said first plurality of conductors, wherein said first-in, first-out memory block further comprises a plurality of control inputs programmably coupled to said first plurality of conductors, wherein said plurality of control inputs control operations of said first-in, first-out memory block, wherein said first-in, first-out memory block generates a plurality of flag outputs programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicate a status of said first-in, first-out memory block.
Claim 15
Dependent Claim
153 words
A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; and a first-in, first-out memory block, programmably coupled to said first plurality of conductors, wherein said first-in, first-out memory block further comprises a plurality of control inputs programmably coupled to said first plurality of conductors, wherein said plurality of control inputs control operations of said first-in, first-out memory block, wherein said first-in, first-out memory block generates a plurality of flag outputs programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicate a status of said first-in, first-out memory block.
Claim 16
Dependent Claim
46 words
A programmable logic device integrated circuit of claim 13 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, said plurality of control inputs for said first-in, first-out memory block.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |