EP0410759A2
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EP
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Configurable logic array and method
Assignee: Xilinx Inc
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Filing: 1990-07-26
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Granted: —
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Expires: 2010-07-26
Abstract
Abstract This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells (C1,1,C1,2,...) which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.
Inventors
- 👤 Ross H. Freeman
- 👤 Hung-Cheng Hsieh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 20:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
71 words
A configurable logic array having a plurality of configurable logic blocks (B1 ,1 ,B1 ,2,...), comprising: means for configuring each configurable logic block by loading memory bits into a plurality of memory cells (C1,1,C1,2,...) associated with the configurable logic block, and means for writing to at least some of the memory cells after configuration of at least some of the remainder of the memory cells associated with the configurable logic block.
Claim 2
Dependent Claim
71 words
A configurable logic array having a plurality of configurable logic blocks (B1 ,1 ,B1 ,2,...), comprising: means for configuring each configurable logic block by loading memory bits into a plurality of memory cells (C1,1,C1,2,...) associated with the configurable logic block, and means for writing to at least some of the memory cells after configuration of at least some of the remainder of the memory cells associated with the configurable logic block.
Claim 3
Dependent Claim
35 words
A configurable logic array as claimed in claim 1 in which the means for writing to at least some of the memory cells (C1,1,C1,2,...) is under control of logic programmed into the configurable logic array.
Claim 4
Dependent Claim
39 words
A configurable logic array as claimed in claim 1 in which each configurable logic block (B1,1,B1,2,...) comprises means for writing to at least some of the memory cells after configuration, thereby providing the configurable logic array with distributed memory.
Claim 5
Dependent Claim
41 words
A configurable logic array as claimed in claim 3 in which the memory cells having means for writing after configuration of the configurable logic blocks can be accessed by others of the configurable logic blocks to serve as random access memory.
Claim 6
Dependent Claim
28 words
A configurable logic array as claimed in claim 1 in which each of the memory cells (C1,1,C1,2,...) includes two nodes for providing output signals complementary to each other.
Claim 7
Dependent Claim
36 words
A configurable logic array as claimed in claim 5 in which each of the memory cells (c1,1,C1,2,...) includes a first access line and a first pass transistor for allowing the memory cell to be read or
Claim 8
Dependent Claim
54 words
A configurable logic array as claimed in claim 6 in which the means for writing to at least some of the memory cells after configuration of the configurable logic block comprises a second access line and a second pass transistor for allowing the memory cell to be written to on the second access line.
Claim 9
Dependent Claim
23 words
A configurable logic array as claimed in claim 1 in which the memory bits represent a truth table for a desired logic function.
Claim 10
Dependent Claim
50 words
A configurable logic array as claimed in claim 1 in which the plurality of memory cells associated with the configurable logic block can be configured to provide a single group of memory bits when addressed and can be configured to provide a plurality of groups of memory bits when addressed.
Claim 11
Independent Claim
66 words
A method of configuring configurable logic blocks of a configurable logic array comprising the steps of: configuring each configurable logic block by loading memory bits into a plurality of memory cells associated with the configurable logic block, and writing to at least some of the memory cells after configuration of at least some of the remainder of the memory cells associated with the configurable logic block.
Claim 12
Independent Claim
66 words
A method of configuring configurable logic blocks of a configurable logic array comprising the steps of: configuring each configurable logic block by loading memory bits into a plurality of memory cells associated with the configurable logic block, and writing to at least some of the memory cells after configuration of at least some of the remainder of the memory cells associated with the configurable logic block.
References Cited (Backward Citations)
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