US7380220B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dummy fill for integrated circuits
Assignee: Cadence Design Systems Inc
•
Filing: 2004-09-22
•
Granted: 2008-05-27
•
Expires: 2024-09-22
Abstract
Abstract A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Inventors
- 👤 Taber H. Smith
- 👤 Vikas Mehrotra
- 👤 David White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 03:01
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; H; H10; H10P; H10P52/00; H10P52/40; H10P52/403; H10P95/00; H10P95/06; H10P95/062; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W20/071; H10W20/092; G06F2119/00; G06F2119/18; H10W20/40; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 80
Claim 1
Independent Claim
202 words
A method for implementing dummy fill in an electronic circuit design of an integrated circuit, comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.
Claim 2
Independent Claim
202 words
A method for implementing dummy fill in an electronic circuit design of an integrated circuit, comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.
Claim 3
Dependent Claim
39 words
The method of claim 1 also including: operating a server to provide dummy fill generation functions for a semiconductor design, and enabling a user at a client to operate through a web browser to develop the dummy fill strategy.
Claim 4
Dependent Claim
14 words
The method of claim 2 in which the server is local to the user.
Claim 5
Dependent Claim
14 words
The method of claim 3 in which the server is remote from the user.
Claim 6
Dependent Claim
52 words
The method of claim 1 also including: analyzing a design to which the dummy fill strategy has been applied, adjusting the design based on the analysis, iterating the analyzing and adjusting steps, and certifying that an integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.
Claim 7
Dependent Claim
38 words
The method of claim 1 also including: defining a set of hierarchical cell placements for dummy fill, and reducing a size of an electronic layout file to which dummy fill is added by using the hierarchical cell placements.
Claim 8
Dependent Claim
24 words
The method of claim 1 in which the dummy fill generation is performed by a user through a web browser and a web server.
Claim 9
Dependent Claim
15 words
The method of claim 7 in which the web server is local to the user.
Claim 10
Dependent Claim
15 words
The method of claim 7 in which the web server is remote from the user.
Claim 11
Dependent Claim
13 words
The method of claim 1 in which the process comprises a damascene process.
Claim 12
Dependent Claim
20 words
The method of claim 1 in which the dummy fill strategy includes determining the size and placement of dummy fill.
Claim 13
Dependent Claim
18 words
The method of claim 1 in which the fabrication process comprises a formation of a low-K interlayer dielectric.
Claim 14
Dependent Claim
19 words
The method of claim 1 in which generating the dummy fill strategy includes dividing a semiconductor design into grids.
Claim 15
Dependent Claim
27 words
The method of claim 13 in which generating the dummy fill strategy also includes extracting local pattern densities for a semiconductor design for each of the grids.
Claim 16
Dependent Claim
30 words
The method of claim 14 , also including using models for computing film thickness non-uniformity with respect to a semiconductor design for which the dummy fill strategy is being generated.
Claim 17
Dependent Claim
13 words
The method of claim 15 also including computing a variation in film thickness.
Claim 18
Dependent Claim
27 words
The method of claim 13 in which generating the dummy fill strategy also includes extracting local line width for a semiconductor design for each of the grids.
Claim 19
Dependent Claim
27 words
The method of claim 13 in which generating the dummy fill strategy also includes extracting local line spacing for a semiconductor design for each of the grids.
Claim 20
Dependent Claim
22 words
The method of claim 13 in which generating the dummy fill strategy also includes computing an effective pattern density for each grid.
Claim 21
Dependent Claim
17 words
The method of claim 13 also including deriving coordinates of all objects within each of the grids.
Claim 22
Dependent Claim
27 words
The method of claim 20 also including generating at least one of line width, line space, length, and bounding box with respect to each of the objects.
Claim 23
Dependent Claim
14 words
The method of claim 20 in which the dummy fill includes slots in objects.
Claim 24
Dependent Claim
23 words
The method of claim 13 in which the dummy fill strategy includes adding dummy fill in empty areas of each of the grids.
Claim 25
Dependent Claim
19 words
The method of claim 23 comprising re-computing a local density in each of the grids after adding dummy fill.
Claim 26
Dependent Claim
21 words
The method of claim 23 also comprising re-computing an effective pattern density for each of the grids after adding dummy fill.
Claim 27
Dependent Claim
20 words
The method of claim 25 in which the effective pattern density is computed based on a polishing process planarization length.
Claim 28
Dependent Claim
21 words
The method of claim 25 in which the effective pattern density is computed using an elliptically weighted window or other filter.
Claim 29
Dependent Claim
22 words
The method of claim 26 in which an effective pattern density is generated dynamically with a change in a process planarization length.
Claim 30
Dependent Claim
45 words
The method of claim 1 in which the dummy fill strategy is based on criteria for electrical parameter variation tolerances for at least one of the following: capacitance and resistance, sheet resistance, outputs delay, skew, voltage drop, drive current loss, dielectric constant or crosstalk noise.
Claim 31
Dependent Claim
12 words
The method of claim 1 in which the fabrication process comprises lithography.
Claim 32
Dependent Claim
13 words
The method of claim 1 in which the fabrication process comprises electrochemical deposition.
Claim 33
Dependent Claim
15 words
The method of claim 1 in which the fabrication process comprises copper chemical mechanical polishing.
Claim 34
Dependent Claim
16 words
The method of claim 1 also including extracting pattern dependencies from a layout of the semiconductor.
Claim 35
Dependent Claim
21 words
The method of claim 33 in which the layout dependencies include with respect to line spacing, line width or line density.
Claim 36
Dependent Claim
29 words
The method of claim 1 also including: using patterned test wafers or semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe.
Claim 37
Dependent Claim
52 words
The method of claim 1 also comprising: using a calibrated pattern dependent model to map pattern dependent features to wafer-state parameters comprising resulting film thickness, film thickness variation, dishing, erosion and electrical parameters, which include sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, or effective dielectric constant.
Claim 38
Dependent Claim
28 words
The method of claim 1 also comprising: using a cost function to measure an impact of dummy fill modification on process induced wafer state and electrical parameter variation.
Claim 39
Dependent Claim
23 words
The method of claim 1 also comprising: predicting an impact of the dummy fill generated by the dummy fill strategy on process variation.
Claim 40
Dependent Claim
43 words
The method of claim 1 also comprising: based on a combination of more than one pattern dependent model and cost function, generating the dummy fill strategy for placement and sizing of dummy fill in a process that optimizes full-chip wafer-state and electrical parameters.
Claim 41
Dependent Claim
37 words
The method of claim 1 also comprising: based on predicted or simulated wafer state and electrical parameters, generating one or more dummy fill rules for use in dummy fill placement and sizing in a semiconductor fabrication process.
Claim 42
Dependent Claim
15 words
The method of claim 40 in which the dummy fill rules include dummy fill sizing.
Claim 43
Dependent Claim
15 words
The method of claim 40 in which the dummy fill rules include dummy fill placement.
Claim 44
Dependent Claim
19 words
The method of claim 40 in which the dummy fill rules include dummy fill hierarchical cell creation and management.
Claim 45
Dependent Claim
32 words
The method of claim 1 also comprising: providing dummy fill functions to generate the dummy fill strategy, and using the functions to automatically modify GDS-format electronic layout files for a semiconductor device.
Claim 46
Dependent Claim
22 words
The method of claim 44 in which the GDS files are modified to improve uniformity and electrical performance of the semiconductor device.
Claim 47
Dependent Claim
14 words
The method of claim 45 in which the process comprises a damascene process flow.
Claim 48
Dependent Claim
47 words
The method of claim 1 also comprising: at an internet server, receiving from a client a layout file for a semiconductor device, generating dummy fill modifications to the layout file at the server, and returning the dummy fill modified layout file from the server to the client.
Claim 49
Dependent Claim
42 words
The method of claim 1 also comprising: at a server, providing a service that enables a user to interactively configure a dummy fill application running on the server, and enabling the user to generate dummy fill information using the dummy fill application.
Claim 50
Dependent Claim
36 words
The method of claim 1 also comprising making available to a user on a network a service that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.
Claim 51
Dependent Claim
32 words
The method of claim 49 in which the dummy fill information that is verified includes at least one of a dummy fill pattern, the dummy fill strategy, or a dummy fill representation.
Claim 52
Dependent Claim
24 words
The method of claim 49 in which the dummy fill information is verified with respect to a single interconnect level of the semiconductor design.
Claim 53
Dependent Claim
23 words
The method of claim 49 in which the dummy fill information is verified with respect to multiple interconnect levels of the semiconductor design.
Claim 54
Dependent Claim
30 words
The method of claim 49 also including: sizing dummy fill objects and creating a dummy fill pattern of the objects for one or more interconnect levels of the semiconductor design.
Claim 55
Dependent Claim
15 words
The method of claim 49 in which the dummy fill information comprises dummy fill rules.
Claim 56
Dependent Claim
16 words
The method of claim 53 in which the pattern includes oxide or metal dummy fill objects.
Claim 57
Dependent Claim
22 words
The method of claim 53 in which the objects of the dummy fill pattern are placed to minimize full-chip film thickness variation.
Claim 58
Dependent Claim
23 words
The method of claim 53 in which the objects of the dummy fill pattern are placed to minimize full-chip variation in electrical parameters.
Claim 59
Dependent Claim
30 words
The method of claim 57 in which the electrical parameters comprise at least one of sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, and effective dielectric constant.
Claim 60
Dependent Claim
41 words
The method of claim 1 also comprising: making available to a user on a network a web-based application comprised of web services that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.
Claim 61
Dependent Claim
25 words
The method of claim 1 in which the dummy fill strategy includes using dummy fill objects to improve a structural integrity of low-K dielectric features.
Claim 62
Dependent Claim
28 words
The method of claim 1 in which the dummy fill strategy includes using dummy fill objects to maintain or improve an effective dielectric constant of low-K dielectric features.
Claim 63
Dependent Claim
21 words
The method of claim 61 in which the effective dielectric constant is maintained through all steps of a damascene process flow.
Claim 64
Dependent Claim
28 words
The method of claim 1 in which the dummy fill strategy includes using dummy fill objects to facilitate integration of low-k dielectric materials into a damascene process flow.
Claim 65
Dependent Claim
39 words
The method of claim 1 also comprising: maintaining a library of semiconductor dummy fill information, and making the library available for use in connection with generating dummy fill placement specifications, and updating the library with changed dummy fill information.
Claim 66
Dependent Claim
39 words
The method of claim 1 also comprising: storing calibration information with respect to at least one of the following: process tools, recipes, and flows, and updating the calibration information to reflect changes in the process tools, recipes or flows.
Claim 67
Dependent Claim
17 words
The method of claim 65 also including using the calibration information in generating the dummy fill strategy.
Claim 68
Dependent Claim
23 words
The method of claim 65 also including selecting among process tools, recipes and flows from calibration database based upon desired dummy fill characteristics.
Claim 69
Dependent Claim
33 words
The method of claim 1 also comprising: enabling a user to obtain the dummy fill strategy for a semiconductor design using a single click of a user interface device through a user interface.
Claim 70
Dependent Claim
26 words
The method of claim 1 also comprising: enabling a user to obtain the dummy fill strategy for a semiconductor design over the internet using web services.
Claim 71
Independent Claim
208 words
An apparatus for implementing dummy fill in an electronic circuit design of an integrated circuit, comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, means for generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; means for using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and means for displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.
Claim 72
Independent Claim
208 words
An apparatus for implementing dummy fill in an electronic circuit design of an integrated circuit, comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, means for generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; means for using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and means for displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.
Claim 73
Dependent Claim
43 words
The apparatus of claim 70 further comprising: means for operating a server to provide dummy fill generation functions for a semiconductor design; and means for enabling a user at a client to operate through a web browser to develop the dummy fill strategy.
Claim 74
Dependent Claim
60 words
The apparatus of claim 70 further comprising: means for analyzing a design to which the dummy fill strategy has been applied, means for adjusting the design based on the analysis, means for iterating the analyzing and adjusting steps, and means for certifying that an integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.
Claim 75
Dependent Claim
31 words
The apparatus of claim 70 further comprising: means for using patterned test wafers or semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe.
Claim 76
Dependent Claim
233 words
A computer-readable medium carrying one or more sequences of instructions, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors for implementing dummy fill in an electronic circuit design of an integrated circuit, the process comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.
Claim 77
Dependent Claim
233 words
A computer-readable medium carrying one or more sequences of instructions, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors for implementing dummy fill in an electronic circuit design of an integrated circuit, the process comprising: based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a dummy fill strategy for placement and sizing of dummy fill in the integrated circuit, in which the dummy fill strategy adds or removes a structure to the electronic circuit design of the integrated circuit, and the pattern dependent model is determined based upon calibration using information from a patterned test wafer or a semiconductor device; using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the placement and sizing of dummy fill in the integrated circuit, wherein the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill strategy, wherein the chemical mechanical polishing process comprising one or more steps that are steps of a fabrication process flow, the fabrication process flow comprising two or more steps of fabrication; and displaying a result of the using the pattern dependent model and the electrical impact analysis to evaluate expected results of dummy fill or storing the result in a tangible machine accessible medium.
Claim 78
Dependent Claim
40 words
The computer-readable medium of claim 74 further comprising: operating a server to provide dummy fill generation functions for a semiconductor design; and enabling a user at a client to operate through a web browser to develop the dummy fill strategy.
Claim 79
Dependent Claim
53 words
The computer-readable medium of claim 74 further comprising: analyzing a design to which the dummy fill strategy has been applied; adjusting the design based on the analysis; iterating the analyzing and adjusting steps; and certifying that an integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.
Claim 80
Dependent Claim
30 words
The computer-readable medium of claim 74 further comprising: using patterned test wafers or semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe.
References Cited (Backward Citations)
US5124927A
Cited
EP0453753A2
Cited
US5903469A
Cited
US5597668A
Cited
US5663076A
Cited
US5821621A
Cited
US5861342A
Cited
US5798298A
Cited
US5972541A
Cited
US5705301A
Cited
US5763955A
Cited
US5923563A
Cited
US5948573A
Cited
US5854125A
Cited
US5920487A
Cited
US5923947A
Cited
US6118137A
Cited
US6578188B1
Cited
US6309956B1
Cited
US6081272A
Cited
US6343370B1
Cited
US6093631A
Cited
US6344409B1
Cited
US6230299B1
Cited
US6049789A
Cited
US6263476B1
Cited
US6176992B1
Cited
US6259115B1
Cited
US6550041B1
Cited
US6255125B1
Cited
US6328872B1
Cited
US20020083401A1
Cited
US6344408B1
Cited
US6249904B1
Cited
US6484300B1
Cited
US6396158B1
Cited
US6124197A
Cited
US6556947B1
Cited
US6323113B1
Cited
US6352623B1
Cited
US20020162082A1
Cited
US20010052107A1
Cited
US6556884B1
Cited
US6380087B1
Cited
US20020037655A1
Cited
US6708318B2
Cited
US6625801B1
Cited
US20020045110A1
Cited
US6671570B2
Cited
US6704920B2
Cited
US6562639B1
Cited
US6358856B1
Cited
US6665856B1
Cited
US6486066B2
Cited
US20020106837A1
Cited
US6567964B2
Cited
US6742165B2
Cited
US20020157076A1
Cited
US6611045B2
Cited
US20030084416A1
Cited
US20030107134A1
Cited
US6708129B1
Cited
WO2003079240A2
Cited
US6751785B1
Cited
US6904581B1
Cited
WO2003079240A3
Cited
US20030199150A1
Cited
US6866571B1
Cited
US20050051809A1
Cited
US20030228714A1
Cited
US20030226757A1
Cited
US20030229479A1
Cited
US20030229875A1
Cited
US20050196964A1
Cited
US20050235246A1
Cited
US7124386B2
Cited
US7152215B2
Cited
US20070101305A1
Cited
US20040044984A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-05-27 | 2011-11-26 | 2012-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-05-27 | 2015-11-26 | 2016-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-05-27 | 2019-11-26 | 2020-05-27 | $7700.00 | Window Closed / Lapsed |