US6323113B1
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Intelligent gate-level fill methods for reducing global pattern density effects
Assignee: NXP BV
•
Filing: 1999-12-10
•
Granted: 2001-11-27
•
Expires: 2019-12-10
Abstract
Abstract The present invention provides methods for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density. A gate layout defining gate areas on the gate layer is provided along with a diffusion layout defining active diffusion areas over a semiconductor substrate. For the gate layout, a pattern density is determined. Then, the areas not occupied by the gate areas and the diffusion areas are determined. Additionally, a range of pattern densities is provided in a set of predefined fill patterns with each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities. Among the set of predefined fill patterns, a predefined fill pattern is selected for producing the target pattern density. Then, the gate layer is filled by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas. In so doing, the target pattern density is provided in the gate layer when combined with the pattern density of the gate layout.
Inventors
- 👤 Calvin T. Gabriel
- 👤 Tammy D. Zheng
- 👤 Subhas Bothra
- 👤 Harlan L. Sur, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D89/00; H10D89/10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
207 words
A method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate areas on the gate layer and the diffusion layout defining active diffusion areas over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; determining the areas not occupied by the gate areas and the diffusion areas; providing a range of pattern densities in a set of predefined fill patterns, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities; and selecting a predefined fill pattern from the set of predefined fill patterns for producing the target pattern density; and filling the gate layer by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas so as to provide the target pattern density in the gate layer when combined with the pattern density of the gate layout wherein the gate layer is filled to the target pattern density only when the pattern density of the gate layout is below 20 percent.
Claim 2
Independent Claim
207 words
A method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate areas on the gate layer and the diffusion layout defining active diffusion areas over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; determining the areas not occupied by the gate areas and the diffusion areas; providing a range of pattern densities in a set of predefined fill patterns, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities; and selecting a predefined fill pattern from the set of predefined fill patterns for producing the target pattern density; and filling the gate layer by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas so as to provide the target pattern density in the gate layer when combined with the pattern density of the gate layout wherein the gate layer is filled to the target pattern density only when the pattern density of the gate layout is below 20 percent.
Claim 3
Dependent Claim
29 words
The method as recited in claim 1 , wherein the gate layer is comprised of a material selected from the group consisting of polysilicon, amorphous silicon, silicide, and metal.
Claim 4
Dependent Claim
26 words
The method as recited in claim 1 , wherein the gate layer is a polysilicon gate layer and the gate layout is a polysilicon gate layout.
Claim 5
Dependent Claim
36 words
The method as recited in claim 1 , further comprising: generating a gate layer layout by combining the selected predefined fill patterns and the gate layout to provide the target pattern density in the gate layer.
Claim 6
Independent Claim
229 words
A method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate areas on the gate layer and the diffusion layout defining active diffusion areas over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; determining the areas not occupied by the gate areas and the diffusion areas, the determining further including, creating a combined union of the gate areas of the gate layout and the diffusion areas and the diffusion layout, and taking an inverse of the combined union so as to generate the areas not occupied by the gate and diffusion areas; providing a range of pattern densities in a set of predefined fill patterns, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities; and selecting a predefined fill pattern from the set of predefined fill patterns for producing the target pattern density; and filling the gate layer by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas so as to provide the target pattern density in the gate layer when combined with the pattern density of the gate layout.
Claim 7
Independent Claim
229 words
A method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate areas on the gate layer and the diffusion layout defining active diffusion areas over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; determining the areas not occupied by the gate areas and the diffusion areas, the determining further including, creating a combined union of the gate areas of the gate layout and the diffusion areas and the diffusion layout, and taking an inverse of the combined union so as to generate the areas not occupied by the gate and diffusion areas; providing a range of pattern densities in a set of predefined fill patterns, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities; and selecting a predefined fill pattern from the set of predefined fill patterns for producing the target pattern density; and filling the gate layer by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas so as to provide the target pattern density in the gate layer when combined with the pattern density of the gate layout.
Claim 8
Dependent Claim
60 words
The method as recited in claim 5 , wherein the inverse of the union representing the areas not occupied by the gate and diffusion areas is sized down by a predetermined amount to provide a buffer region to ensure that the dummy fill patterns of the selected predefined fill pattern do not contact the gate areas and the diffusion areas.
Claim 9
Dependent Claim
19 words
The method as recited in claim 6 , wherein the predetermined amount is between 0.2 μm and 50 μm.
Claim 10
Dependent Claim
43 words
The method as recited in claim 5 , wherein the predefined fill pattern is selected b iterating through the set of predefined fill patterns and determining the associated pattern densities that are generated when combined with the pattern density of the gate layout.
Claim 11
Independent Claim
199 words
A method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate areas on the gate layer and the diffusion layout defining active diffusion areas over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; determining the areas not occupied by the gate areas and the diffusion areas; providing a range of pattern densities in a set of predefined fill patterns wherein the predefined fill patterns provide the pattern density range between 5 percent and 50 percent, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities; and selecting a predefined fill pattern from the set of predefined fill patterns for producing the target pattern density; and filling the gate layer by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas so as to provide the target pattern density in the gate layer when combined with the pattern density of the gate layout.
Claim 12
Independent Claim
199 words
A method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate areas on the gate layer and the diffusion layout defining active diffusion areas over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; determining the areas not occupied by the gate areas and the diffusion areas; providing a range of pattern densities in a set of predefined fill patterns wherein the predefined fill patterns provide the pattern density range between 5 percent and 50 percent, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities; and selecting a predefined fill pattern from the set of predefined fill patterns for producing the target pattern density; and filling the gate layer by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas so as to provide the target pattern density in the gate layer when combined with the pattern density of the gate layout.
Claim 13
Dependent Claim
29 words
The method as recited in claim 9 , wherein the gate layer is comprised of a material selected from the group consisting of polysilicon, amorphous silicon, silicide, and metal.
Claim 14
Dependent Claim
26 words
The method as recited in claim 9 , wherein the gate layer is a polysilicon gate layer and the gate layout is a polysilicon gate layout.
Claim 15
Dependent Claim
36 words
The method as recited in claim 9 , further comprising: generating a gate layer layout by combining the selected predefined fill patterns and the gate layout to provide the target pattern density in the gate layer.
Claim 16
Dependent Claim
231 words
An automated method for identifying dummy fill locations in a gate layer to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; creating combined union regions of the gate regions and the diffusion regions; taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions; providing a set of predefined fill patterns associated with a range of pattern densities wherein the set of predefined fill patterns are configured to be placed in the regions not occupied by the gate and diffusion regions for determining the associated pattern densities in combination with the pattern density of the gate layout, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; iterating through the set of predefined fill patterns and selecting a predefined fill pattern for generating the target pattern density; and locating the dummy fill patterns of the selected predefined fill pattern in the identified regions that are not occupied by the gate and diffusion regions, wherein the located dummy fill patterns produce the target pattern density in the gate layer when combined with the gate regions.
Claim 17
Dependent Claim
231 words
An automated method for identifying dummy fill locations in a gate layer to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; creating combined union regions of the gate regions and the diffusion regions; taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions; providing a set of predefined fill patterns associated with a range of pattern densities wherein the set of predefined fill patterns are configured to be placed in the regions not occupied by the gate and diffusion regions for determining the associated pattern densities in combination with the pattern density of the gate layout, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; iterating through the set of predefined fill patterns and selecting a predefined fill pattern for generating the target pattern density; and locating the dummy fill patterns of the selected predefined fill pattern in the identified regions that are not occupied by the gate and diffusion regions, wherein the located dummy fill patterns produce the target pattern density in the gate layer when combined with the gate regions.
Claim 18
Dependent Claim
29 words
The method as recited in claim 13 , wherein the gate layer is comprised of a material selected from the group consisting of polysilicon, amorphous silicon, silicide, and metal.
Claim 19
Dependent Claim
26 words
The method as recited in claim 13 , wherein the gate layer is a polysilicon gate layer and the gate layout is a polysilicon gate layout.
Claim 20
Dependent Claim
16 words
The method as recited in claim 13 , wherein the diffusion regions are active diffusion regions.
Claim 21
Dependent Claim
230 words
An automated method for identifying dummy fill locations in a gate layer to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; creating combined union regions of the gate regions and the diffusion regions; taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions wherein the inverse of the combined union regions is sized down by a predetermined amount to provide a buffer region to ensure that the located dummy fill patterns do not contact the gate regions and the diffusion regions; providing a set of predefined fill patterns associated with a range of pattern densities, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; iterating through the set of predefined fill patterns and selecting a predefined fill pattern for generating the target pattern density; and locating the dummy fill patterns of the selected predefined fill pattern in the identified regions that are not occupied by the gate and diffusion regions, wherein the located dummy fill patterns produce the target pattern density in the gate layer when combined with the gate regions.
Claim 22
Dependent Claim
230 words
An automated method for identifying dummy fill locations in a gate layer to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; creating combined union regions of the gate regions and the diffusion regions; taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions wherein the inverse of the combined union regions is sized down by a predetermined amount to provide a buffer region to ensure that the located dummy fill patterns do not contact the gate regions and the diffusion regions; providing a set of predefined fill patterns associated with a range of pattern densities, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; iterating through the set of predefined fill patterns and selecting a predefined fill pattern for generating the target pattern density; and locating the dummy fill patterns of the selected predefined fill pattern in the identified regions that are not occupied by the gate and diffusion regions, wherein the located dummy fill patterns produce the target pattern density in the gate layer when combined with the gate regions.
Claim 23
Dependent Claim
26 words
The method as recited in claim 17 , wherein the located dummy fill patterns are filled in the gate layer to provide the target pattern density.
Claim 24
Dependent Claim
36 words
The method as recited in claim 17 , wherein a gate layer layout is generated by combining the located dummy fill patterns with the gate regions to provide the target pattern density in the gate layer.
Claim 25
Dependent Claim
33 words
The method as recited in claim 19 , wherein the gate layer layout having the target pattern density is generated only when the pattern density of the gate layout is below 20 percent.
Claim 26
Dependent Claim
19 words
The method as recited in claim 17 , wherein the predetermined amount is between 0.2 μm and 50 μm.
Claim 27
Dependent Claim
211 words
An automated method for identifying dummy fill locations in a gate layer to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; creating combined union regions of the gate regions and the diffusion regions; taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions; providing a set of predefined fill patterns associated with a range of pattern densities wherein the predefined fill patterns are adapted to provide the pattern density range between 5 percent and 50 percent, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; iterating through the set of predefined fill patterns and selecting a predefined fill pattern for generating the target pattern density; and locating the dummy fill patterns of the selected predefined fill pattern in the identified regions that are not occupied by the gate and diffusion regions, wherein the located dummy fill patterns produce the target pattern density in the gate layer when combined with the gate regions.
Claim 28
Dependent Claim
211 words
An automated method for identifying dummy fill locations in a gate layer to produce a target pattern density, comprising: providing a gate layout and a diffusion layout, the gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; determining a pattern density of the gate layout over the semiconductor substrate; creating combined union regions of the gate regions and the diffusion regions; taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions; providing a set of predefined fill patterns associated with a range of pattern densities wherein the predefined fill patterns are adapted to provide the pattern density range between 5 percent and 50 percent, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; iterating through the set of predefined fill patterns and selecting a predefined fill pattern for generating the target pattern density; and locating the dummy fill patterns of the selected predefined fill pattern in the identified regions that are not occupied by the gate and diffusion regions, wherein the located dummy fill patterns produce the target pattern density in the gate layer when combined with the gate regions.
Claim 29
Dependent Claim
36 words
The method as recited in claim 22 , wherein a gate layer layout is generated by combining the located dummy fill patterns with the gate regions to provide the target pattern density in the gate layer.
Claim 30
Dependent Claim
29 words
The method as recited in claim 22 , wherein the gate layer is comprised of a material selected from the group consisting of polysilicon, amorphous silicon, silicide, and metal.
Claim 31
Dependent Claim
26 words
The method as recited in claim 22 , wherein the gate layer is a polysilicon gate layer and the gate layout is a polysilicon gate layout.
Claim 32
Independent Claim
159 words
A method for filling a gate layer to a target fill pattern density from a diffusion fill pattern, the diffusion fill pattern defining dummy fill pattern regions over a semiconductor substrate, the method comprising: providing a gate layout defining gate regions over the semiconductor substrate; combining the dummy fill pattern regions and the gate regions to produce a combined union area; determining a pattern density of the combined union area; resizing the diffusion fill pattern in response to the determined pattern density to generate resized diffusion fill pattern regions to be filled for producing the target fill pattern density wherein the diffusion fill pattern is sized down when the resized dummy fill pattern regions to be filled is less than the dummy fill pattern regions; and filling the resized diffusion fill pattern regions to provide the target fill pattern density in the gate layer when combined with the gate regions so as to substantially reduce global pattern density effects.
Claim 33
Independent Claim
159 words
A method for filling a gate layer to a target fill pattern density from a diffusion fill pattern, the diffusion fill pattern defining dummy fill pattern regions over a semiconductor substrate, the method comprising: providing a gate layout defining gate regions over the semiconductor substrate; combining the dummy fill pattern regions and the gate regions to produce a combined union area; determining a pattern density of the combined union area; resizing the diffusion fill pattern in response to the determined pattern density to generate resized diffusion fill pattern regions to be filled for producing the target fill pattern density wherein the diffusion fill pattern is sized down when the resized dummy fill pattern regions to be filled is less than the dummy fill pattern regions; and filling the resized diffusion fill pattern regions to provide the target fill pattern density in the gate layer when combined with the gate regions so as to substantially reduce global pattern density effects.
Claim 34
Dependent Claim
27 words
The method as recited in claim 26 , wherein a gate layer layout is generated by combining the resized diffusion fill pattern regions with the gate regions.
Claim 35
Dependent Claim
34 words
The method as recited in claim 27 , wherein the gate layer layout having the target fill pattern density is generated only when the pattern density of the gate layout is below 20 percent.
Claim 36
Dependent Claim
44 words
The method as recited in claim 26 , wherein the combined union area is used in combination with the gate regions to produce the target fill pattern density when the pattern density of the combined union area is between 20 percent and 30 percent.
Claim 37
Dependent Claim
31 words
The method as recited in claim 29 , wherein the combined union area of the dummy fill pattern regions and the gate regions is used without resizing the diffusion fill pattern.
Claim 38
Independent Claim
159 words
A method for filling a gate layer to a target fill pattern density from a diffusion fill pattern, the diffusion fill pattern defining dummy fill pattern regions over a semiconductor substrate, the method comprising: providing a gate layout defining gate regions over the semiconductor substrate; combining the dummy fill pattern regions and the gate regions to produce a combined union area; determining a pattern density of the combined union area; resizing the diffusion fill pattern in response to the determined pattern density to generate resized diffusion fill pattern regions to be filled for producing the target fill pattern density wherein the diffusion fill pattern is sized up when the resized dummy fill pattern regions to be filled is greater than the dummy fill pattern regions; and filling the resized diffusion fill pattern regions to provide the target fill pattern density in the gate layer when combined with the gate regions so as to substantially reduce global pattern density effects.
Claim 39
Independent Claim
159 words
A method for filling a gate layer to a target fill pattern density from a diffusion fill pattern, the diffusion fill pattern defining dummy fill pattern regions over a semiconductor substrate, the method comprising: providing a gate layout defining gate regions over the semiconductor substrate; combining the dummy fill pattern regions and the gate regions to produce a combined union area; determining a pattern density of the combined union area; resizing the diffusion fill pattern in response to the determined pattern density to generate resized diffusion fill pattern regions to be filled for producing the target fill pattern density wherein the diffusion fill pattern is sized up when the resized dummy fill pattern regions to be filled is greater than the dummy fill pattern regions; and filling the resized diffusion fill pattern regions to provide the target fill pattern density in the gate layer when combined with the gate regions so as to substantially reduce global pattern density effects.
Claim 40
Dependent Claim
29 words
The method as recited in claim 31 , wherein the gate layer is comprised of a material selected from the group consisting of polysilicon, amorphous silicon, silicide, and metal.
Claim 41
Dependent Claim
26 words
The method as recited in claim 31 , wherein the gate layer is a polysilicon gate layer and the gate layout is a polysilicon gate layout.
Claim 42
Dependent Claim
36 words
The method as recited in claim 31 , wherein the diffusion fill pattern is sized down by shrinking the diffusion fill pattern when the pattern density of the combined union area is greater than 30 percent.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-26 | 2005-05-28 | 2005-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-26 | 2009-05-28 | 2009-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-26 | 2013-05-28 | 2013-11-27 | $7700.00 | Window Closed / Lapsed |