US5160995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor IC device with dummy wires
Assignee: Toshiba Corp
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Filing: 1991-07-25
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Granted: 1992-11-03
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Expires: 2011-07-25
Abstract
Abstract A plurality of cells providing constituent elements for a semiconductor integrated circuit are provided in and on a major surface of a semiconductor substrate of a semiconductor integrated circuit chip. A plurality of wires are each provided between a cell and a cell to provide cell-to-cell wires. A plurality of dummy wires are connected to an internal power source terminal of a second power source potential which is different from a first power source terminal. A capacitance is created between the dummy wire and the semiconductor substrate to prevent a voltage fluctuation at the power source. The dummy wires are selectively cut off the internal power source terminal of the second potential to correct a wrong connection line or a signal delay time.
Inventors
- 👤 Satoshi Wada
- 👤 Shinichi Wakabayashi
- 👤 Masayo Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:41
CPC Classifications
H; H10; H10D; H10D84/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W20/01; H10W20/495
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
187 words
A semiconductor integrated circuit device comprising: a semiconductor integrated circuit chip including a semiconductor substrate to which a first power source potential is supplied; at least two cell arrays each extending in a longitudinal direction, and each having a plurality of cells arranged in parallel on a major surface of said semiconductor substrate; a plurality of cell-to-cell wires in a region between said at least two cell arrays, said cell-to-cell wires extending in the longitudinal direction; a plurality of dummy wires in the region between said at least two cell arrays, said dummy wires extending in the longitudinal direction, said dummy wires having the same pitch and width parallel to the major surface and transverse to the longitudinal direction as the cell-to-cell wires, and said dummy wires being connected to an internal power source terminal having a second power source potential which is different from the first power source potential; and a connection layer connected to the second power source potential and said dummy wires, the connection layer being transverse to the dummy wires; wherein said dummy wires provide means for stabilizing the second power source potential.
Claim 2
Dependent Claim
187 words
A semiconductor integrated circuit device comprising: a semiconductor integrated circuit chip including a semiconductor substrate to which a first power source potential is supplied; at least two cell arrays each extending in a longitudinal direction, and each having a plurality of cells arranged in parallel on a major surface of said semiconductor substrate; a plurality of cell-to-cell wires in a region between said at least two cell arrays, said cell-to-cell wires extending in the longitudinal direction; a plurality of dummy wires in the region between said at least two cell arrays, said dummy wires extending in the longitudinal direction, said dummy wires having the same pitch and width parallel to the major surface and transverse to the longitudinal direction as the cell-to-cell wires, and said dummy wires being connected to an internal power source terminal having a second power source potential which is different from the first power source potential; and a connection layer connected to the second power source potential and said dummy wires, the connection layer being transverse to the dummy wires; wherein said dummy wires provide means for stabilizing the second power source potential.
Claim 3
Dependent Claim
21 words
The semiconductor circuit device according to claim 1, wherein said semiconductor integrated circuit is formed by an automatic array connection system.
Claim 4
Dependent Claim
44 words
The semiconductor circuit device according to claim 1, wherein said dummy wires and second power source potential terminal are connected by a specific cell for their own connection only and the specific cell is incorporated into said cell array of the semiconductor integrated circuit.
Claim 5
Dependent Claim
173 words
A semiconductor integrated circuit device, comprising: a semiconductor integrated circuit chip including a semiconductor substrate to which a first power source potential is supplied; at least two cell arrays each extending in a longitudinal direction, and each having a plurality of cells arranged in parallel on a major surface of said semiconductor substrate; a plurality of cell-to-cell wires in a region between said at least two cell arrays, said cell-to-cell wires extending in the longitudinal direction; and a plurality of dummy wires in the region between said at least two cell arrays, said dummy wires extending in the longitudinal direction, said dummy wires having the same pitch and width parallel to the major surface and transverse to the longitudinal direction as the cell-to-cell wires, and said dummy wires being connected to an internal power source terminal having a second power source potential which is different from the first power source potential; wherein said dummy wires simultaneously provide means for repairing wires and for mitigating unevenness on a surface of the semiconductor integrated circuit.
Claim 6
Dependent Claim
173 words
A semiconductor integrated circuit device, comprising: a semiconductor integrated circuit chip including a semiconductor substrate to which a first power source potential is supplied; at least two cell arrays each extending in a longitudinal direction, and each having a plurality of cells arranged in parallel on a major surface of said semiconductor substrate; a plurality of cell-to-cell wires in a region between said at least two cell arrays, said cell-to-cell wires extending in the longitudinal direction; and a plurality of dummy wires in the region between said at least two cell arrays, said dummy wires extending in the longitudinal direction, said dummy wires having the same pitch and width parallel to the major surface and transverse to the longitudinal direction as the cell-to-cell wires, and said dummy wires being connected to an internal power source terminal having a second power source potential which is different from the first power source potential; wherein said dummy wires simultaneously provide means for repairing wires and for mitigating unevenness on a surface of the semiconductor integrated circuit.
Claim 7
Dependent Claim
18 words
The semiconductor integrated circuit device according to claim 4, wherein said dummy wires provide means for delay correction.
Claim 8
Dependent Claim
22 words
The semiconductor integrated circuit device according to claim 5, wherein said dummy wires provide means for stabilizing the second power source potential.
Claim 9
Dependent Claim
34 words
A semiconductor integrated circuit device according to claim 4, further comprising a connection layer connected to the second power source potential and said dummy wires, the connection layer being transverse to the dummy wires.
References Cited (Backward Citations)
JPS59198796A
Cited
JPS60119749A
Cited
JPS61125045A
Cited
JPS62206855A
Cited
US4916514A
Cited
US4958222A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |