US5923947A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for achieving low capacitance diffusion pattern filling
Assignee: NXP BV
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Filing: 1997-05-06
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Granted: 1999-07-13
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Expires: 2017-05-06
Abstract
Abstract An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the active diffusion regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.
Inventors
- 👤 Harlan Sur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:19
CPC Classifications
H; H10; H10D; H10D89/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
136 words
An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate, the method comprising the steps of: a) determining the location of active diffusion regions on a semiconductor substrate; b) determining the location of interconnect lines on said semiconductor substrate; c) creating a union of said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate; and d) utilizing said union created in step c) to define allowable locations for placement of fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed under said interconnect lines said fill pattern diffusion regions adapted to provide a more consistent diffusion pattern density and said fill pattern diffusion regions adapted to enhance planarity in subsequent planarization processes.
Claim 2
Dependent Claim
136 words
An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate, the method comprising the steps of: a) determining the location of active diffusion regions on a semiconductor substrate; b) determining the location of interconnect lines on said semiconductor substrate; c) creating a union of said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate; and d) utilizing said union created in step c) to define allowable locations for placement of fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed under said interconnect lines said fill pattern diffusion regions adapted to provide a more consistent diffusion pattern density and said fill pattern diffusion regions adapted to enhance planarity in subsequent planarization processes.
Claim 3
Dependent Claim
62 words
The automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate as recited in claim 1 wherein step a) further comprises the steps of: a1) determining the location of active diffusion regions of a first conductivity type on said semiconductor substrate; and a2) determining the location of active diffusion regions of a second conductivity type on said semiconductor substrate.
Claim 4
Dependent Claim
52 words
The automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate as recited in claim 1 wherein step c) further comprises: creating said union by logically ORing said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate.
Claim 5
Dependent Claim
72 words
The automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate as recited in claim 1 wherein step d) further comprises: utilizing said union created in step c) in an automated pattern generator to define said allowable locations for placement of said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed, by said automated pattern generator, under said interconnect lines.
Claim 6
Independent Claim
203 words
A method for generating a diffusion pattern mask which selectively locates fill pattern diffusion regions on a semiconductor substrate, the diffusion pattern mask generation method comprising the steps of: a) determining the location of active diffusion regions on a semiconductor substrate; b) determining the location of interconnect lines on said semiconductor substrate; c) creating a union of said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate; d) utilizing said union created in step c) to determine allowable locations for placement of fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed under said interconnect lines; and e) using said union created in step c) and said allowable locations determined in step d) to generate a diffusion mask layer wherein said diffusion mask layer locates said active diffusion regions, said interconnect lines, and said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions do not underlie said interconnect lines said fill pattern diffusion regions adapted to provide a more consistent diffusion pattern density and said fill pattern diffusion regions adapted to enhance planarity in subsequent planarization processes.
Claim 7
Independent Claim
203 words
A method for generating a diffusion pattern mask which selectively locates fill pattern diffusion regions on a semiconductor substrate, the diffusion pattern mask generation method comprising the steps of: a) determining the location of active diffusion regions on a semiconductor substrate; b) determining the location of interconnect lines on said semiconductor substrate; c) creating a union of said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate; d) utilizing said union created in step c) to determine allowable locations for placement of fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed under said interconnect lines; and e) using said union created in step c) and said allowable locations determined in step d) to generate a diffusion mask layer wherein said diffusion mask layer locates said active diffusion regions, said interconnect lines, and said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions do not underlie said interconnect lines said fill pattern diffusion regions adapted to provide a more consistent diffusion pattern density and said fill pattern diffusion regions adapted to enhance planarity in subsequent planarization processes.
Claim 8
Dependent Claim
56 words
The method for generating a diffusion pattern mask as recited in claim 5 wherein step a) further comprises the steps of: a1) determining the location of active diffusion regions of a first conductivity type on said semiconductor substrate; and a2) determining the location of active diffusion regions of a second conductivity type on said semiconductor substrate.
Claim 9
Dependent Claim
50 words
T he method for generating a diffusion pattern mask as recited in claim 5 wherein step c) further comprises the steps of: creating said union by logically ORing said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate.
Claim 10
Dependent Claim
69 words
The method for generating a diffusion pattern mask as recited in claim 5 wherein step d) further comprises the steps of: utilizing said union created in step c) in an automated pattern generator to define said allowable locations for placement of said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed, by said automated pattern generator, under said interconnect lines.
References Cited (Backward Citations)
US5104823A
Cited
US5037771A
Cited
US5256564A
Cited
US5434089A
Cited
US5462882A
Cited
US5627083A
Cited
US5663076A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |