US6611045B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming an integrated circuit device using dummy features and structure thereof
Assignee: NXP USA Inc
•
Filing: 2001-06-04
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Granted: 2003-08-26
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Expires: 2021-06-04
Abstract
Abstract A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.
Inventors
- 👤 Edward O. Travis
- 👤 Sejal N. Chheda
- 👤 Ruiqi Tian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:19
CPC Classifications
H; H10; H10P; H10P50/00; H10P95/00; H10P95/06; H10P95/062; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
136 words
An integrated circuit device, comprising: a semiconductor substrate; a first active feature in the semiconductor substrate, wherein the first active feature has a first width; a second active feature in the semiconductor substrate, wherein the second active features has a second width substantially smaller than the first active feature; a first dummy-available region in the semiconductor substrate separating the first active feature from the second active feature by at least 20 microns, wherein the first dummy available-region is void of any active features; a first dummy feature in the first dummy-available region and in close proximity to the second active feature; and a second dummy-available region in the first dummy-available region separating the first dummy feature from the first active feature by at least 20 microns, wherein the second dummy-available region is void of dummy features.
Claim 2
Dependent Claim
136 words
An integrated circuit device, comprising: a semiconductor substrate; a first active feature in the semiconductor substrate, wherein the first active feature has a first width; a second active feature in the semiconductor substrate, wherein the second active features has a second width substantially smaller than the first active feature; a first dummy-available region in the semiconductor substrate separating the first active feature from the second active feature by at least 20 microns, wherein the first dummy available-region is void of any active features; a first dummy feature in the first dummy-available region and in close proximity to the second active feature; and a second dummy-available region in the first dummy-available region separating the first dummy feature from the first active feature by at least 20 microns, wherein the second dummy-available region is void of dummy features.
Claim 3
Dependent Claim
24 words
The integrated circuit device of claim 1 , wherein the second active feature and the first dummy feature are separated by a first distance.
Claim 4
Dependent Claim
31 words
The integrated circuit device of claim 2 , further comprising: a plurality of dummy features surrounding the second active feature and separated from the second active feature by the first distance.
Claim 5
Dependent Claim
27 words
The integrated circuit device of claim 3 further comprising a second dummy feature in the first dummy-available region and in close proximity to the first active feature.
Claim 6
Dependent Claim
20 words
The integrated circuit device of claim 1 , wherein the first active feature comprises a plurality of high-density active features.
Claim 7
Dependent Claim
29 words
The integrated circuit device of claim 1 , wherein the first dummy feature has a third width, the third width being at least as large as the second width.
Claim 8
Dependent Claim
17 words
The integrated circuit device of claim 6 , wherein the third width is at least one micron.
Claim 9
Dependent Claim
20 words
The integrated circuit device of claim 7 , wherein the first active feature comprises a plurality of high-density active features.
Claim 10
Dependent Claim
27 words
The integrated circuit device of claim 8 further comprising a second dummy feature in the first dummy-available region and in close proximity to the first active feature.
Claim 11
Dependent Claim
48 words
The integrated circuit device of claim 9 , wherein the second active feature and the first dummy feature are separated by a first distance and further comprising: a plurality of dummy features surrounding the second active feature and separated from the second active feature by the first distance.
Claim 12
Dependent Claim
20 words
The integrated circuit device of claim 1 , wherein the second active feature comprises a plurality of high-density active features.
Claim 13
Dependent Claim
76 words
An integrated circuit device, comprising: a first active feature region free from polishing dummy features; a polishing dummy feature region having a first polishing dummy feature density adjacent to and surrounding the first active feature region; and a dummy-available region adjacent to at least a portion of the polishing dummy feature region having a second polishing dummy feature density, wherein the second polishing dummy feature density is substantially less than the first polishing dummy feature density.
Claim 14
Dependent Claim
76 words
An integrated circuit device, comprising: a first active feature region free from polishing dummy features; a polishing dummy feature region having a first polishing dummy feature density adjacent to and surrounding the first active feature region; and a dummy-available region adjacent to at least a portion of the polishing dummy feature region having a second polishing dummy feature density, wherein the second polishing dummy feature density is substantially less than the first polishing dummy feature density.
Claim 15
Dependent Claim
20 words
The integrated circuit device of claim 12 , wherein the first active feature region is less than 400 square microns.
Claim 16
Dependent Claim
18 words
The integrated circuit device of claim 13 , wherein the dummy-available region is at least 400 square microns.
Claim 17
Dependent Claim
19 words
The integrated circuit device of claim 14 , wherein the integrated circuit device is partially populated with active features.
Claim 18
Dependent Claim
27 words
The integrated circuit device of claim 15 , wherein the polishing dummy feature region comprises at least rows of dummy features surrounding the first active feature region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-08-25 | 2007-02-24 | 2007-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-08-25 | 2011-02-24 | 2011-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-08-25 | 2015-02-24 | 2015-08-26 | $7700.00 | Window Closed / Lapsed |