US6448630B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device comprising a polish preventing pattern
Assignee: Mitsubishi Electric Corp
•
Filing: 1999-04-15
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Granted: 2002-09-10
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Expires: 2019-04-15
Abstract
Abstract A semiconductor device having a polish preventing pattern that can improve the planarity of an element formation region after the CMP method polishing is provided. To the shape of an element formation region, a loop-shaped element formation region dummy is formed in a uniform width and at a uniform distance from the edge of the element formation region to have a loop shape. That can prevent formation of such a portion that is on a line extended from a gap between polish preventing patterns as well as a large gap between an element formation region and a polish preventing pattern. Accordingly, local application of large pressure to an end of an element formation region is suppressed which is caused when a polishing cloth bends. As a result, the semiconductor device does not have a locally substantially etched portion. The planarity of the surface of an element formation region is maintained in the semiconductor device.
Inventors
- 👤 Shigeki Komori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:39
CPC Classifications
H; H10; H10W; H10W42/00; H10P; H10P95/00; H10P95/06; H10P95/062; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
42 words
A semiconductor device comprising a polish preventing pattern surrounding an element formation region, formed at a main surface of a semiconductor substrate, in a substantially continuous manner at an almost uniform distance horizontally from an outer edge of said element formation region.
Claim 2
Dependent Claim
42 words
A semiconductor device comprising a polish preventing pattern surrounding an element formation region, formed at a main surface of a semiconductor substrate, in a substantially continuous manner at an almost uniform distance horizontally from an outer edge of said element formation region.
Claim 3
Dependent Claim
44 words
The semiconductor device according to claim 1 , wherein said polish preventing pattern includes a remainder of said main surface of said semiconductor substrate, which is adjacent to a trench formed around said element formation region at said main surface of said semiconductor substrate.
Claim 4
Dependent Claim
31 words
The semiconductor device according to claim 2 , wherein an insulation film is filled in said trench between the outer edge of said element formation region and said polish preventing pattern.
Claim 5
Dependent Claim
23 words
The semiconductor device according to claim 1 , wherein said polish preventing pattern is formed at a prescribed distance from a conductive layer.
Claim 6
Dependent Claim
27 words
The semiconductor device according to claim 1 , wherein said polish preventing pattern is formed at a prescribed distance from a boundary of an impurity diffusion region.
Claim 7
Dependent Claim
40 words
The semiconductor device according to claim 1 , wherein said polish preventing pattern further includes a polish preventing pattern for well-potential fixation formed to horizontally surround a well and fixed in potential by another electrode to fix the well potential.
Claim 8
Dependent Claim
24 words
The semiconductor device according to claim 1 , wherein said polish preventing pattern includes a loop-shaped polish preventing pattern extending in a band shape.
Claim 9
Dependent Claim
34 words
The semiconductor device according to claim 7 , wherein said polish preventing pattern includes a concavity formation preventing pattern formed at a distance from said loop-shaped polish preventing pattern with an insulation film therebetween.
Claim 10
Dependent Claim
23 words
The semiconductor device according to claim 8 , wherein a pad for receiving signals is further formed on said concavity formation preventing pattern.
Claim 11
Dependent Claim
18 words
The semiconductor device according to claim 7 , wherein said loop-shaped polish preventing pattern has a discontinuous portion.
Claim 12
Dependent Claim
25 words
The semiconductor device according to claim 7 , wherein said polish preventing pattern includes another loop-shaped polish preventing pattern outside said loop-shaped polish preventing pattern.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-09 | 2006-03-11 | 2006-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-09 | 2010-03-11 | 2010-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-09 | 2014-03-11 | 2014-09-10 | $7700.00 | Window Closed / Lapsed |