US5459096A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating a semiconductor device using dual planarization layers
Assignee: Motorola Solutions Inc
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Filing: 1994-07-05
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Granted: 1995-10-17
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Expires: 2014-07-05
Abstract
Abstract An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.
Inventors
- 👤 Suresh Venkatesan
- 👤 Stephen Poon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:06
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; Y; Y10; Y10S; Y10S148/00; Y10S148/005; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
96 words
A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having elevated and recessed regions therein, wherein a first planarization layer overlies the elevated regions and a dielectric layer overlies the recessed regions; depositing a fill material to overlie the first planarization layer and the dielectric layer; etching the fill material to expose portions of the first planarization layer overlying the elevated regions; forming a second planarization layer to overlie the fill material and the selected portions of the first planarization layer; and planarizing the substrate to form a smooth surface.
Claim 2
Dependent Claim
96 words
A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having elevated and recessed regions therein, wherein a first planarization layer overlies the elevated regions and a dielectric layer overlies the recessed regions; depositing a fill material to overlie the first planarization layer and the dielectric layer; etching the fill material to expose portions of the first planarization layer overlying the elevated regions; forming a second planarization layer to overlie the fill material and the selected portions of the first planarization layer; and planarizing the substrate to form a smooth surface.
Claim 3
Dependent Claim
23 words
The process of claim 1, wherein the step of providing a semiconductor substrate comprises oxidizing the recessed regions to form the dielectric layer.
Claim 4
Dependent Claim
20 words
The process of claim 1, wherein the step of depositing a fill material comprises chemical vapor deposition of silicon dioxide.
Claim 5
Dependent Claim
34 words
The process of claim 1, wherein the step of forming a second planarization layer comprises depositing a layer selected from the group consisting of silicon nitride, boron nitride, silicon-rich silicon nitride, and boron oxynitride.
Claim 6
Dependent Claim
87 words
A process for fabricating a semiconductor device comprising the steps of: providing a substrate having elevated and recessed regions therein; oxidizing the recessed regions to form a dielectric liner overlying the recessed regions; forming a fill material overlying the elevated regions and filling the recessed regions; removing a portion of the fill material overlying the elevated regions; forming an etch stop layer overlying the elevated regions and the fill material; and removing portions of the etch stop layer and the fill material to form a planar surface.
Claim 7
Dependent Claim
87 words
A process for fabricating a semiconductor device comprising the steps of: providing a substrate having elevated and recessed regions therein; oxidizing the recessed regions to form a dielectric liner overlying the recessed regions; forming a fill material overlying the elevated regions and filling the recessed regions; removing a portion of the fill material overlying the elevated regions; forming an etch stop layer overlying the elevated regions and the fill material; and removing portions of the etch stop layer and the fill material to form a planar surface.
Claim 8
Dependent Claim
48 words
The process of claim 5 further comprising the steps of: etching away remaining portions of the etch stop layer; and forming a gate dielectric layer on the elevated regions of the substrate, such that the dielectric liner remains intermediate to the gate dielectric layer and the fill material.
Claim 9
Dependent Claim
34 words
The process of claim 5, wherein the step of forming an etch stop layer comprises depositing a layer selected from the group consisting of silicon nitride, boron nitride, silicon-rich silicon nitride, and boron oxynitride.
Claim 10
Dependent Claim
20 words
The process of claim 5, wherein the step of forming a fill material comprises chemical vapor deposition of silicon dioxide.
Claim 11
Dependent Claim
22 words
The process of claim 5, wherein the step of removing portions of the etch stop layer and the fill material comprises chemical-mechanical-polishing.
Claim 12
Dependent Claim
123 words
A process for fabricating a semiconductor device comprising the steps of: providing a substrate having a first planarization layer overlying the substrate, the first planarization layer having an opening therein exposing a portion of the substrate; etching the substrate to form a trench in the exposed portion of the substrate; oxidizing the substrate to form a dielectric liner overlying the trench; depositing a fill material to overlie the first planarization layer and to fill the trench; etching the fill material to expose portions of the first planarization layer; depositing a second planarization layer to overlie the fill material and the exposed portions of the first planarization layer; and polishing back the second planarization layer and the fill material to form a planar surface.
Claim 13
Dependent Claim
123 words
A process for fabricating a semiconductor device comprising the steps of: providing a substrate having a first planarization layer overlying the substrate, the first planarization layer having an opening therein exposing a portion of the substrate; etching the substrate to form a trench in the exposed portion of the substrate; oxidizing the substrate to form a dielectric liner overlying the trench; depositing a fill material to overlie the first planarization layer and to fill the trench; etching the fill material to expose portions of the first planarization layer; depositing a second planarization layer to overlie the fill material and the exposed portions of the first planarization layer; and polishing back the second planarization layer and the fill material to form a planar surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-16 | 1999-04-17 | 1999-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-16 | 2003-04-17 | 2003-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-16 | 2007-04-17 | 2007-10-17 | $7700.00 | Window Closed / Lapsed |