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US5256592A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating a semiconductor integrated circuit device

Assignee: Lapis Semiconductor Co Ltd
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Filing: 1992-08-11
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Granted: 1993-10-26
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Expires: 2012-08-11
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Abstract

Abstract A method of the invention comprises the step of forming on part of a silicon substrate (101) a three-layered film consisting of a first silicon nitride film (102), a first silicon oxide film (103) and a second silicon nitride film (104) and forming a third silicon nitride film (106) on side wall portions of the three-layered film, the step of etchiing an exposed silicon substrate (101) to form a first groove having substantially vertical side walls and refilling the first groove with a silicon oxide film (108), and the step of removing the second and third silicon nitride films (104,106) to form a second groove (111) having substantially vertical side walls relative to the silicon substrate (101) exposed by the removal. Accordingly, the second groove (111) which serves as a trench groove by self alignment is formed an end portion of the silicon oxide film (108) within a field region (107) as having a structure which is in direct contact with an element forming region (115). In addition, the groove width is constant as a width of the third silicon nitride film (106), thus permitting the parasitic capacitance between the collector and the substrate to be minimized.

Inventors

  • 👤 Ikuya Matsushita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 03:51
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/693; H10P50/695; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 166 words
A method for fabricating a semiconductor integrated circuit device comprising (a) the step of forming, on an element forming region on a surface of a silicon substrate, a three-layered film comprising of a first silicon nitride film, a first silicon oxide film and a second silicon nitride film; (b) the step of forming a third silicon nitride film on side walls of the three-layered film; (c) the step of anisotropically etching an exposed silicon substrate through the second and third silicon nitride films as a mask to form a first groove having substantially vertical side walls with respect to the semiconductor substrate and refilling the first groove with a second silicon oxide film; and (d) the step of removing the second and third silicon nitride films and forming a second groove having side walls substantially vertical with respect to the semiconductor substrate exposed by the removal of the third silicon nitride film by anisotropic etching through the first and second silicon oxide films as a mask.
Claim 2
Independent Claim 166 words
A method for fabricating a semiconductor integrated circuit device comprising (a) the step of forming, on an element forming region on a surface of a silicon substrate, a three-layered film comprising of a first silicon nitride film, a first silicon oxide film and a second silicon nitride film; (b) the step of forming a third silicon nitride film on side walls of the three-layered film; (c) the step of anisotropically etching an exposed silicon substrate through the second and third silicon nitride films as a mask to form a first groove having substantially vertical side walls with respect to the semiconductor substrate and refilling the first groove with a second silicon oxide film; and (d) the step of removing the second and third silicon nitride films and forming a second groove having side walls substantially vertical with respect to the semiconductor substrate exposed by the removal of the third silicon nitride film by anisotropic etching through the first and second silicon oxide films as a mask.
Claim 3
Independent Claim 220 words
A method for fabricating a semiconductor integrated circuit device comprising (a) the step of forming, on an element forming region on a surface of a silicon substrate, a three-layered film comprising a first silicon nitride film, a first silicon oxide film and a second silicon nitride film; (b) the step of forming a third silicon nitride film on side walls of the three-layered film; (c) the step of anisotropically etching an exposed silicon substrate through the second and third silicon nitride films as a mask to form a first groove having substantially vertical side walls with respect to the semiconductor substrate and refilling the first groove with a second silicon oxide film; (d) the step of removing the second and third silicon nitride films and forming a second groove having side walls substantially vertical with respect to the semiconductor substrate exposed by the removal of the third silicon nitride film by anisotropic etching through the first and second silicon oxide films as a mask; (e) the step of forming a third silicon oxide film on the second groove; (f) the step of forming a polysilicon layer on the third silicon oxide film; and (g) the step of converting an upper surface of the polysilicon layer into a fourth silicon oxide film through a mask of the second silicon nitride layer.
Claim 4
Independent Claim 220 words
A method for fabricating a semiconductor integrated circuit device comprising (a) the step of forming, on an element forming region on a surface of a silicon substrate, a three-layered film comprising a first silicon nitride film, a first silicon oxide film and a second silicon nitride film; (b) the step of forming a third silicon nitride film on side walls of the three-layered film; (c) the step of anisotropically etching an exposed silicon substrate through the second and third silicon nitride films as a mask to form a first groove having substantially vertical side walls with respect to the semiconductor substrate and refilling the first groove with a second silicon oxide film; (d) the step of removing the second and third silicon nitride films and forming a second groove having side walls substantially vertical with respect to the semiconductor substrate exposed by the removal of the third silicon nitride film by anisotropic etching through the first and second silicon oxide films as a mask; (e) the step of forming a third silicon oxide film on the second groove; (f) the step of forming a polysilicon layer on the third silicon oxide film; and (g) the step of converting an upper surface of the polysilicon layer into a fourth silicon oxide film through a mask of the second silicon nitride layer.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-10-25 1997-04-26 1997-10-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-10-25 2001-04-26 2001-10-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-10-25 2005-04-26 2005-10-26 $7700.00 Window Closed / Lapsed

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