US6013937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buffer layer for improving control of layer thickness
Assignee: Infineon Technologies AG
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Filing: 1997-09-26
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Granted: 2000-01-11
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Expires: 2017-09-26
Abstract
Abstract A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.
Inventors
- 👤 Jochen Beintner
- 👤 Ulrike Gruening
- 👤 Carl Radens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:11
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0387; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/694; H10P14/6943; H10P14/69433; H10P50/00; H10P50/69; H10P50/691; H10P50/692; H10W10/041; H10W10/40; H10B12/0385; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
192 words
A semiconductor chip fabricated by the method of: providing a semiconductor chip having a pad layer disposed on a semiconductor substrate; forming a dielectric layer on the pad layer; forming a buffer layer on the dielectric layer, the buffer layer being made from different material than the dielectric layer; forming a mask layer on the buffer layer, the mask layer being made from different material than the buffer layer; forming at least one trench in the semiconductor chip, each trench being formed in a portion of a top surface of the semiconductor chip through the mask, buffer, and dielectric layers, and through a portion of the substrate; depositing a filler in the at least one trench and on the top surface; polishing the filler from the top surface to expose a portion of the mask layer; forming at least one dielectric collar in the at least one trench; etching the exposed portion of the mask layer after formation of said dielectric collar, to expose a portion of the buffer layer; and removing the exposed portion of the buffer layer after etching said mask layer, to expose a portion of the dielectric layer.
Claim 2
Dependent Claim
192 words
A semiconductor chip fabricated by the method of: providing a semiconductor chip having a pad layer disposed on a semiconductor substrate; forming a dielectric layer on the pad layer; forming a buffer layer on the dielectric layer, the buffer layer being made from different material than the dielectric layer; forming a mask layer on the buffer layer, the mask layer being made from different material than the buffer layer; forming at least one trench in the semiconductor chip, each trench being formed in a portion of a top surface of the semiconductor chip through the mask, buffer, and dielectric layers, and through a portion of the substrate; depositing a filler in the at least one trench and on the top surface; polishing the filler from the top surface to expose a portion of the mask layer; forming at least one dielectric collar in the at least one trench; etching the exposed portion of the mask layer after formation of said dielectric collar, to expose a portion of the buffer layer; and removing the exposed portion of the buffer layer after etching said mask layer, to expose a portion of the dielectric layer.
Claim 3
Dependent Claim
19 words
A semiconductor device fabricated as in claim 1, wherein the pad layer includes a plurality of buffer layers therethrough.
Claim 4
Dependent Claim
29 words
A semiconductor device fabricated as in claim 1, wherein the buffer layer is made from TEOS and the mask layer and the dielectric layer are made from silicon nitride.
Claim 5
Dependent Claim
18 words
A semiconductor device fabricated as in claim 1, wherein the buffer layer is less than 100 angstroms thick.
Claim 6
Dependent Claim
19 words
A semiconductor device fabricated as in claim 1, wherein the buffer layer is between 50 and 100 angstroms thick.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |