Patent FR1031675A successfully refreshed from Google Patents.
US6344409B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dummy patterns for aluminum chemical polishing (CMP)
Assignee: Qimonda AG
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Filing: 2000-03-14
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Granted: 2002-02-05
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Expires: 2020-03-14
Abstract
Abstract A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.
Inventors
- 👤 Mark A. Jaso
- 👤 Rainer F. Schnabel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:59
CPC Classifications
H; H10; H10P; H10P76/00; H10P52/00; H10P52/40; H10P52/403; Y; Y10; Y10S; Y10S438/00; Y10S438/926
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
179 words
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer, said method comprising: dividing each chip on the wafer into a plurality of regions; determining the metal density for each region of each chip based on the circuit pattern for that region; adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum noted density for each region; forming both the desired circuit pattern and any dummy circuit pattern as openings in adielectric layer on each chip; coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; and polishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.
Claim 2
Dependent Claim
179 words
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer, said method comprising: dividing each chip on the wafer into a plurality of regions; determining the metal density for each region of each chip based on the circuit pattern for that region; adding a dummy circuit pattern to each region on each chip to provide at least a minimum metal density in each region or setting a maximum and/or minimum noted density for each region; forming both the desired circuit pattern and any dummy circuit pattern as openings in adielectric layer on each chip; coating the patterned dielectric layer with a layer of metal which metal fills the openings forming the desired circuit pattern and any dummy circuit pattern and covers the surface of the wafer including the circuit patterns; and polishing the metal coated wafer until no metal remains outside the desired and any dummy circuit patterns.
Claim 3
Dependent Claim
15 words
The program storage device of claim 1 wherein the maximum metal density is about 60-90%.
Claim 4
Dependent Claim
15 words
The program storage device of claim 2 wherein the minimum metal density is about 20-50%.
Claim 5
Dependent Claim
18 words
The program storage device of claim 1 wherein each chip is divided into up to about 1,000 regions.
Claim 6
Dependent Claim
12 words
The program storage device of claim 4 wherein the regions are square.
Claim 7
Dependent Claim
32 words
The program storage device of claim 1 wherein dummy circuit patterns or the setting of a maximum and/or minimum metal density are provided for chip fragments at the edge of the wafer.
Claim 8
Independent Claim
105 words
An apparatus for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprises: a rotatable turntable assembly; a polishing pad supported on said assembly; a rotatable carrier located above said assembly and adapted to hold a silicon wafer during planarizing and positioned between said carrier and said polishing pad; and means for changing the metal density of metal across the surface of the wafer by either setting a high metal density pattern factor design limit and/or a low metal density pattern factor design limit or by using a dummy circuit design on the wafer surface.
Claim 9
Independent Claim
105 words
An apparatus for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer comprises: a rotatable turntable assembly; a polishing pad supported on said assembly; a rotatable carrier located above said assembly and adapted to hold a silicon wafer during planarizing and positioned between said carrier and said polishing pad; and means for changing the metal density of metal across the surface of the wafer by either setting a high metal density pattern factor design limit and/or a low metal density pattern factor design limit or by using a dummy circuit design on the wafer surface.
Claim 10
Dependent Claim
13 words
An apparatus of claim 7 wherein the maximum metal density is about 60-90%.
Claim 11
Dependent Claim
13 words
The apparatus of claim 8 wherein the minimum metal density is about 20-50%.
Claim 12
Dependent Claim
16 words
The apparatus of claim 7 wherein each chip is divided into up to about 1,000 regions.
Claim 13
Dependent Claim
10 words
The apparatus of claim 10 wherein the regions are square.
Claim 14
Dependent Claim
30 words
The apparatus of claim 7 wherein dummy circuit patterns or the setting of a maximum and/or minimum metal density are provided for chip fragments at the edge of the wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-04 | 2005-08-06 | 2006-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-04 | 2009-08-06 | 2010-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-04 | 2013-08-06 | 2014-02-05 | $7700.00 | Window Closed / Lapsed |