US5899706A
Expired / Lapsed
US
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Method of reducing loading variation during etch processing
Assignee: Infineon Technologies AG
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Filing: 1997-06-30
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Granted: 1999-05-04
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Expires: 2017-06-30
Abstract
Abstract In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.
Inventors
- 👤 Andreas Kluwe
- 👤 Lars Liebmann
- 👤 Frank Prein
- 👤 Thomas Zell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; Y; Y10; Y10S; Y10S438/00; Y10S438/926
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
98 words
A method of manufacturing a DRAM chip comprising: determining the pattern density of the region within the chip having the most densely packed electrically functional devices; adding patterns in regions of the chip that have a pattern density which is less than that of the pattern density of the most densely packed electrically functional devices; and/or adding blockers in regions having higher density as a result of non-electrically functional devices, wherein adding the blockers and patterns result in a more consistent pattern density across the chip to result in a more uniform across chip line width during etching.
Claim 2
Independent Claim
98 words
A method of manufacturing a DRAM chip comprising: determining the pattern density of the region within the chip having the most densely packed electrically functional devices; adding patterns in regions of the chip that have a pattern density which is less than that of the pattern density of the most densely packed electrically functional devices; and/or adding blockers in regions having higher density as a result of non-electrically functional devices, wherein adding the blockers and patterns result in a more consistent pattern density across the chip to result in a more uniform across chip line width during etching.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |