US7339235B1
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Semiconductor device having SOI structure and manufacturing method thereof
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 2000-08-09
•
Granted: 2008-03-04
•
Expires: 2020-08-09
Abstract
Abstract A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.
Inventors
- 👤 Shunpei Yamazaki
- 👤 Hisashi Ohtani
- 👤 Jun Koyama
- 👤 Takeshi Fukunaga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; B; B82; B82Y; B82Y10/00; H10D30/01; H10D30/014; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D86/00; H10D86/01; H10D86/201
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
205 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the first or second impurity regions have dot patterns.
Claim 2
Dependent Claim
205 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the first or second impurity regions have dot patterns.
Claim 3
Dependent Claim
211 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the first or second impurity regions have linear patterns substantially parallel with a channel direction.
Claim 4
Dependent Claim
211 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the first or second impurity regions have linear patterns substantially parallel with a channel direction.
Claim 5
Dependent Claim
219 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising the semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the channel forming regions of the first transistor and the second transistor comprise a plurality of carrier moving regions comprising the semiconductor material.
Claim 6
Dependent Claim
219 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is an n-channel transistor and the second transistor is a p-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising the semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15, and wherein the channel forming regions of the first transistor and the second transistor comprise a plurality of carrier moving regions comprising the semiconductor material.
Claim 7
Dependent Claim
205 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is a p-channel transistor and the second transistor is an n-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 15 and the second impurity element belongs to group 13, and wherein the first or second impurity regions have dot patterns.
Claim 8
Dependent Claim
205 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is a p-channel transistor and the second transistor is an n-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 15 and the second impurity element belongs to group 13, and wherein the first or second impurity regions have dot patterns.
Claim 9
Dependent Claim
211 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is a p-channel transistor and the second transistor is an n-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 15 and the second impurity element belongs to group 13, and wherein the first or second impurity regions have linear patterns substantially parallel with a channel direction.
Claim 10
Dependent Claim
211 words
A semiconductor device having a stacked CMOS circuit comprising: a first layer comprising at least one first transistor; a second layer comprising at least one second transistor over the first layer; wherein each of the first and second transistors comprises: a channel forming region; a source region; a drain region; and a gate electrode, wherein the first transistor is a p-channel transistor and the second transistor is an n-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in the channel forming region of the first transistor, wherein a plurality of second impurity regions each comprising a semiconductor material and a second impurity element are included at least in the channel forming region of the second transistor, wherein each of the plurality of first impurity regions is formed in a part of the channel forming region in the first transistor, wherein each of the plurality of second impurity regions is formed in a part of the channel forming region in the second transistor, wherein the first impurity element belongs to group 15 and the second impurity element belongs to group 13, and wherein the first or second impurity regions have linear patterns substantially parallel with a channel direction.
Claim 11
Dependent Claim
152 words
A semiconductor device having a Bi-CMOS circuit comprising; a bipolar transistor; an insulating film over the at least one bipolar transistor; and an n-channel transistor and a p-channel transistor over the insulating film; wherein each of the n-channel transistor and the p-channel transistor comprises: a semiconductor layer comprising: a channel forming region; a source region; and a drain region; a gate insulating film; and a gate electrode; wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in a part of the channel forming region of the n-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a second impurity element are included at least in a part of the channel forming region of the p-channel transistor, and wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15.
Claim 12
Dependent Claim
152 words
A semiconductor device having a Bi-CMOS circuit comprising; a bipolar transistor; an insulating film over the at least one bipolar transistor; and an n-channel transistor and a p-channel transistor over the insulating film; wherein each of the n-channel transistor and the p-channel transistor comprises: a semiconductor layer comprising: a channel forming region; a source region; and a drain region; a gate insulating film; and a gate electrode; wherein a plurality of first impurity regions each comprising a semiconductor material and a first impurity element are included at least in a part of the channel forming region of the n-channel transistor, wherein a plurality of first impurity regions each comprising a semiconductor material and a second impurity element are included at least in a part of the channel forming region of the p-channel transistor, and wherein the first impurity element belongs to group 13 and the second impurity element belongs to group 15.
Claim 13
Dependent Claim
68 words
A semiconductor device having a Bi-CMOS circuit comprising; a first layer comprising at least one bipolar transistor; a second layer comprising at least one n-channel transistor and one p-channel transistor over the first layer; wherein each of the n-channel transistor and the p-channel transistor comprises; a semiconductor layer comprising: a channel forming region; a source region; and a drain region; a gate insulating film; and a gate electrode.
Claim 14
Dependent Claim
68 words
A semiconductor device having a Bi-CMOS circuit comprising; a first layer comprising at least one bipolar transistor; a second layer comprising at least one n-channel transistor and one p-channel transistor over the first layer; wherein each of the n-channel transistor and the p-channel transistor comprises; a semiconductor layer comprising: a channel forming region; a source region; and a drain region; a gate insulating film; and a gate electrode.
Claim 15
Dependent Claim
67 words
An electric apparatus comprising the semiconductor device according to claim 7 , wherein the electric apparatus is selected from the group consisting of a liquid crystal display device, an EL display device, a CL display device, a TV camera, a personal computer, a car navigation apparatus, a TV projection apparatus, a video camera, and a portable information terminal apparatus including a cellular telephone and a mobile computer.
Claim 16
Dependent Claim
12 words
An EL device having the semiconductor device according to claim 7 .
Claim 17
Dependent Claim
16 words
A semiconductor device according to claim 7 , wherein the semiconductor layer comprises single crystal silicon.
Claim 18
Dependent Claim
16 words
A semiconductor device according to claim 7 , wherein the second layer has a SOI structure.
Claim 19
Dependent Claim
113 words
A semiconductor device having a Bi-CMOS circuit comprising; at least one bipolar transistor; an insulating film over the at least one bipolar transistor; and at least one n-channel transistor and one p-channel transistor over the insulating film; wherein each of the n-channel transistor and the p-channel transistor comprises: a semiconductor layer comprising: a channel forming region; a source region; and a drain region; a gate insulating film; and a gate electrode; wherein a plurality of impurity regions each comprising a semiconductor material and an impurity element are included at least in the channel forming region, wherein each of the plurality of impurity regions is formed in a part of the channel forming region.
Claim 20
Dependent Claim
113 words
A semiconductor device having a Bi-CMOS circuit comprising; at least one bipolar transistor; an insulating film over the at least one bipolar transistor; and at least one n-channel transistor and one p-channel transistor over the insulating film; wherein each of the n-channel transistor and the p-channel transistor comprises: a semiconductor layer comprising: a channel forming region; a source region; and a drain region; a gate insulating film; and a gate electrode; wherein a plurality of impurity regions each comprising a semiconductor material and an impurity element are included at least in the channel forming region, wherein each of the plurality of impurity regions is formed in a part of the channel forming region.
Claim 21
Dependent Claim
67 words
An electric apparatus comprising the semiconductor device according to claim 12 , wherein the electric apparatus is selected from the group consisting of a liquid crystal display device, an EL display device, a CL display device, a TV camera, a personal computer, a car navigation apparatus, a TV projection apparatus, a video camera, and a portable information terminal apparatus including a cellular telephone and a mobile computer.
Claim 22
Dependent Claim
12 words
An EL device having the semiconductor device according to claim 12 .
Claim 23
Dependent Claim
16 words
A semiconductor device according to claim 12 , wherein the semiconductor layer comprises single crystal silicon.
Claim 24
Dependent Claim
16 words
A semiconductor device according to claim 12 , wherein the second layer has a SOI structure.
Claim 25
Dependent Claim
16 words
A semiconductor device according to claim 12 , wherein the impurity element belongs to group 13.
Claim 26
Dependent Claim
14 words
A semiconductor device according to claim 17 , wherein the impurity element is boron.
Claim 27
Dependent Claim
16 words
A semiconductor device according to claim 12 , wherein the impurity element belongs to group 15.
Claim 28
Dependent Claim
16 words
A semiconductor device according to claim 19 , wherein the impurity element is phosphorus or arsenic.
Claim 29
Dependent Claim
58 words
A semiconductor device according to claim 12 , wherein a width W of the channel forming region, a total width W pi of the impurity regions, and a total width W pa of regions between the impurity regions satisfy relationships W pi /W=0.1 to 0.9, W pa /W=0.1 to 0.9, and W pi /W pa =1/9 to 9.
Claim 30
Dependent Claim
33 words
A semiconductor device according to claim 12 , wherein a total width of regions other than the impurity regions in the channel forming region is within a range of 30 to 3,000 Å.
Claim 31
Dependent Claim
15 words
A semiconductor device according to claim 12 , wherein the impurity regions have dot patterns.
Claim 32
Dependent Claim
21 words
A semiconductor device according to claim 12 , wherein the impurity regions have linear patterns substantially parallel with a channel direction.
Claim 33
Dependent Claim
29 words
A semiconductor device according to claim 12 , wherein the impurity element in the impurity regions is at a concentration of 1×10 17 to 1×10 20 atoms/cm 3 .
Claim 34
Dependent Claim
20 words
A semiconductor device according to claim 12 , further comprising a plurality of carrier moving regions comprising a semiconductor material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-03-04 | 2011-09-03 | 2012-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-03-04 | 2015-09-03 | 2016-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-03-04 | 2019-09-03 | 2020-03-04 | $7700.00 | Window Closed / Lapsed |