US5606191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with lightly doped drain regions
Assignee: Promos Technologies Inc
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Filing: 1995-04-14
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Granted: 1997-02-25
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Expires: 2015-04-14
Abstract
Abstract A method and structure therefor for the formation of lightly doped drain regions, typically used in the manufacture of a field effect devices. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 20 degrees and greater from a perpendicular to the gate electrodes into both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well, and a buried region in the N type well. Sidewall spacers are then formed on edges of the gate electrodes. An N type implant step is then performed on the P type well region to form the source/drain region of a NMOS device. The method then performs two separate P type implants into the N type well, each at different angles and dosages, to form the P type LDD source/drain region for a PMOS device. The PMOS device includes the buried region which acts as a punchthrough stop, typically used to decrease short channel effects.
Inventors
- 👤 Chih-Hsien Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
436 words
A semiconductor integrated circuit device comprising: a semiconductor substrate, said semiconductor substrate comprising a first upper surface; a first well region having first conductivity type impurities defined on said substrate, said first well region comprising: a first gate electrode formed overlying a gate dielectric, said gate dielectric layer defined overlying said first upper surface on said first well region, said first gate electrode including a first sidewall spacer formed thereon; and a first source/drain region comprising a first LDD region and a first source/drain, said first source/drain having a portion adjacent to said first upper surface, said first source/drain portion adjacent to said first upper surface underlying a portion of said first sidewall spacer, said first LDD region being formed adjacent to said first gate electrode, said first LDD region including a portion adjacent to said first upper surface, said first LDD region portion adjacent to said upper surface having a portion underlying said first gate electrode and a portion underlying said first sidewall spacer; wherein said first LDD region portion underlying said first gate electrode is longer in a lateral direction than said first LDD portion underlying said first sidewall spacer; and a second well region having second conductivity type impurities defined on said substrate, said second well region comprising: a second gate electrode formed overlying a gate dielectric, said gate dielectric defined overlying said second upper surface on said second well region, said second gate electrode including a second sidewall spacer formed thereon; a second source/drain region comprising a second LDD region and a second source/drain, said second source/drain having a portion adjacent to said second upper surface, said second source/drain portion adjacent to said second upper surface underlying a portion of said second sidewall spacer, said second LDD region being formed adjacent to said second gate electrode, said second LDD region including a portion adjacent to said second upper surface, said second LDD portion adjacent to said second upper surface having a portion underlying said second gate electrode and a portion underlying said second sidewall spacer; a pocket region comprising second conductivity type impurities, said pocket region being defined adjacent to said second source/drain, being defined substantially underlying said second LDD region and being defined substantially away from said second upper surface; a channel region comprising first conductivity type impurities formed underlying a portion of said second gate electrode and adjacent to and connected to said second LDD region, said channel region being substantially free from said pocket region; and wherein said second LDD region portion underlying said second gate electrode is longer than said second LDD portion underlying said second sidewall spacer.
Claim 2
Dependent Claim
436 words
A semiconductor integrated circuit device comprising: a semiconductor substrate, said semiconductor substrate comprising a first upper surface; a first well region having first conductivity type impurities defined on said substrate, said first well region comprising: a first gate electrode formed overlying a gate dielectric, said gate dielectric layer defined overlying said first upper surface on said first well region, said first gate electrode including a first sidewall spacer formed thereon; and a first source/drain region comprising a first LDD region and a first source/drain, said first source/drain having a portion adjacent to said first upper surface, said first source/drain portion adjacent to said first upper surface underlying a portion of said first sidewall spacer, said first LDD region being formed adjacent to said first gate electrode, said first LDD region including a portion adjacent to said first upper surface, said first LDD region portion adjacent to said upper surface having a portion underlying said first gate electrode and a portion underlying said first sidewall spacer; wherein said first LDD region portion underlying said first gate electrode is longer in a lateral direction than said first LDD portion underlying said first sidewall spacer; and a second well region having second conductivity type impurities defined on said substrate, said second well region comprising: a second gate electrode formed overlying a gate dielectric, said gate dielectric defined overlying said second upper surface on said second well region, said second gate electrode including a second sidewall spacer formed thereon; a second source/drain region comprising a second LDD region and a second source/drain, said second source/drain having a portion adjacent to said second upper surface, said second source/drain portion adjacent to said second upper surface underlying a portion of said second sidewall spacer, said second LDD region being formed adjacent to said second gate electrode, said second LDD region including a portion adjacent to said second upper surface, said second LDD portion adjacent to said second upper surface having a portion underlying said second gate electrode and a portion underlying said second sidewall spacer; a pocket region comprising second conductivity type impurities, said pocket region being defined adjacent to said second source/drain, being defined substantially underlying said second LDD region and being defined substantially away from said second upper surface; a channel region comprising first conductivity type impurities formed underlying a portion of said second gate electrode and adjacent to and connected to said second LDD region, said channel region being substantially free from said pocket region; and wherein said second LDD region portion underlying said second gate electrode is longer than said second LDD portion underlying said second sidewall spacer.
Claim 3
Dependent Claim
13 words
The device of claim 1 wherein said pocket region is a punchthrough stopper.
Claim 4
Dependent Claim
21 words
The device of claim 1 wherein said pocket region and said first LDD regions were formed during a same implant step.
Claim 5
Dependent Claim
25 words
The device of claim 1 wherein said first conductivity type impurities are a P type and said second conductivity type impurities are an N type.
Claim 6
Dependent Claim
13 words
The device of claim 4 wherein said pocket region is said N type.
Claim 7
Dependent Claim
23 words
The device of claim 1 wherein said first LDD portion underlying said first gate electrode extends to a length of about 0.09 μm.
Claim 8
Dependent Claim
23 words
The device of claim 1 wherein said second LDD portion underlying said second gate electrode extends to a length of about 0.115 μm.
Claim 9
Dependent Claim
217 words
A semiconductor integrated circuit, said semiconductor integrated circuit comprising: a semiconductor substrate having an upper surface; a well region defined in said semiconductor substrate; a gate electrode formed overlying a gate dielectric, said gate dielectric being defined overlying said upper surface on said well region; a sidewall spacer defined on an edge of said gate electrode and defined overlying a portion of said gate dielectric; a lightly doped drain (LDD) region formed adjacent to said gate electrode and extending to said upper surface, said LDD region having a portion underlying said gate electrode and a portion underlying said sidewall spacer; a source/drain region having first conductivity type impurities defined within a portion of said LDD region and extending to said upper surface, said source/drain region having a portion underlying said sidewall spacer and a portion for a source/drain contact; a channel region having first conductivity type impurities formed underlying a portion of said gate electrode and adjacent to said LDD region; and a pocket region having second conductivity type impurities, said pocket region being defined adjacent to said source/drain region and being defined substantially underlying said LDD region, said pocket region being defined substantially outside said channel region; wherein said LDD region portion underlying said gate electrode is longer than said LDD portion underlying said sidewall spacer.
Claim 10
Dependent Claim
217 words
A semiconductor integrated circuit, said semiconductor integrated circuit comprising: a semiconductor substrate having an upper surface; a well region defined in said semiconductor substrate; a gate electrode formed overlying a gate dielectric, said gate dielectric being defined overlying said upper surface on said well region; a sidewall spacer defined on an edge of said gate electrode and defined overlying a portion of said gate dielectric; a lightly doped drain (LDD) region formed adjacent to said gate electrode and extending to said upper surface, said LDD region having a portion underlying said gate electrode and a portion underlying said sidewall spacer; a source/drain region having first conductivity type impurities defined within a portion of said LDD region and extending to said upper surface, said source/drain region having a portion underlying said sidewall spacer and a portion for a source/drain contact; a channel region having first conductivity type impurities formed underlying a portion of said gate electrode and adjacent to said LDD region; and a pocket region having second conductivity type impurities, said pocket region being defined adjacent to said source/drain region and being defined substantially underlying said LDD region, said pocket region being defined substantially outside said channel region; wherein said LDD region portion underlying said gate electrode is longer than said LDD portion underlying said sidewall spacer.
Claim 11
Dependent Claim
19 words
The circuit of claim 1 wherein said channel region is provided with a length of 0.35 microns and less.
Claim 12
Dependent Claim
14 words
The circuit of claim 1 wherein said first conductivity type impurities are P type.
Claim 13
Dependent Claim
14 words
The circuit of claim 1 wherein said second conductivity type impurities are N type.
Claim 14
Dependent Claim
16 words
The circuit of claim 1 wherein said pocket region is provided during an LDD implant step.
Claim 15
Dependent Claim
16 words
The circuit of claim 1 wherein said channel region is substantially free from said pocket region.
Claim 16
Dependent Claim
17 words
The circuit of claim 1 wherein said channel region has a length of 0.4 micron and less.
Claim 17
Dependent Claim
16 words
The circuit of claim 1 further comprising a second well region of second conductivity type impurities.
Claim 18
Dependent Claim
201 words
A CMOS device, said CMOS device comprising: a semiconductor substrate of first conductivity type impurities; a well region of second conductivity type impurities defined in said substrate; a gate electrode formed overlying a gate dielectric on said well region; a sidewall spacer defined on an edge of said gate electrode; a lightly doped drain (LDD) region formed adjacent to said gate electrode, said LDD region having a portion underlying said gate electrode and a portion underlying said sidewall spacer; a source/drain region having second conductivity type impurities defined within a portion of said LDD region, said source/drain region having a portion underlying said sidewall spacer and a portion for a source/drain contact; a channel region having second conductivity type impurities formed underlying a portion of said second gate electrode and formed adjacent to said LDD portion, said channel region having a channel length of 0.4 micron and less; a pocket region having first conductivity type impurities, said pocket region defined adjacent to said source/drain region and substantially underlying said LDD region, said pocket region being substantially free from said channel region; wherein said LDD region portion underlying said gate electrode is laterally longer than said LDD portion underlying said sidewall spacer.
Claim 19
Dependent Claim
201 words
A CMOS device, said CMOS device comprising: a semiconductor substrate of first conductivity type impurities; a well region of second conductivity type impurities defined in said substrate; a gate electrode formed overlying a gate dielectric on said well region; a sidewall spacer defined on an edge of said gate electrode; a lightly doped drain (LDD) region formed adjacent to said gate electrode, said LDD region having a portion underlying said gate electrode and a portion underlying said sidewall spacer; a source/drain region having second conductivity type impurities defined within a portion of said LDD region, said source/drain region having a portion underlying said sidewall spacer and a portion for a source/drain contact; a channel region having second conductivity type impurities formed underlying a portion of said second gate electrode and formed adjacent to said LDD portion, said channel region having a channel length of 0.4 micron and less; a pocket region having first conductivity type impurities, said pocket region defined adjacent to said source/drain region and substantially underlying said LDD region, said pocket region being substantially free from said channel region; wherein said LDD region portion underlying said gate electrode is laterally longer than said LDD portion underlying said sidewall spacer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |