US5334870A
Expired / Lapsed
US
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Complementary MIS transistor and a fabrication process thereof
Assignee: Denso Corp
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Filing: 1993-04-16
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Granted: 1994-08-02
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Expires: 2013-04-16
Abstract
Abstract A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.
Inventors
- 👤 Mitsutaka Katada
- 👤 Hidetoshi Muramoto
- 👤 Seizi Fuzino
- 👤 Tadashi Hattori
- 👤 Katsunori Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:17
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
233 words
A complementary MIS transistor, comprising: a substrate; a P-type well and an N-type well defined in said substrate; an insulating gate provided on each of said P-type well and said N-type well; a source region and a drain region both of N-type and formed in said P-type well so as to align respectively to a first edge and a second, opposite edge of said insulating gate that is provided on said P-type well; a source region and a drain region both of P-type and formed in said N-type well so as to align respectively to a first edge and a second, opposite edge of said insulating gate that is provided on said N-type well; and N-type diffusion regions formed in correspondence to said source region and said drain region in each of said P-type well and said N-type well, said N-type diffusion region having an impurity concentration level that is higher than an impurity concentration level of said P-type well and said N-type well but is lower than an impurity concentration level of said source and drain regions, said N-type diffusion regions extending laterally from said source and drain regions into a part of said substrate located immediately below said first and second edges of said insulating gate, said N-type diffusion regions extending vertically in said substrate to a depth smaller than or equal to a depth of said source and drain regions.
Claim 2
Dependent Claim
233 words
A complementary MIS transistor, comprising: a substrate; a P-type well and an N-type well defined in said substrate; an insulating gate provided on each of said P-type well and said N-type well; a source region and a drain region both of N-type and formed in said P-type well so as to align respectively to a first edge and a second, opposite edge of said insulating gate that is provided on said P-type well; a source region and a drain region both of P-type and formed in said N-type well so as to align respectively to a first edge and a second, opposite edge of said insulating gate that is provided on said N-type well; and N-type diffusion regions formed in correspondence to said source region and said drain region in each of said P-type well and said N-type well, said N-type diffusion region having an impurity concentration level that is higher than an impurity concentration level of said P-type well and said N-type well but is lower than an impurity concentration level of said source and drain regions, said N-type diffusion regions extending laterally from said source and drain regions into a part of said substrate located immediately below said first and second edges of said insulating gate, said N-type diffusion regions extending vertically in said substrate to a depth smaller than or equal to a depth of said source and drain regions.
Claim 3
Dependent Claim
82 words
A complementary MIS transistor as claimed in claim 1, wherein said N-type diffusion regions formed in said N-type well include a sub-diffusion region of P-type such that said sub-diffusion region has a lateral extension and a vertical depth that are smaller than a lateral extension and a vertical depth of said N-type diffusion regions, said sub-diffusion region has an impurity concentration level that is lower than an impurity concentration level of said P-type source and drain regions formed in said N-type well.
Claim 4
Dependent Claim
39 words
A complementary MIS transistor as claimed in claim 1, wherein said N-type diffusion regions has a lateral extension that is larger than a lateral extension of said source and drain regions, at a depth of 0.5 μm or less.
Claim 5
Dependent Claim
45 words
A complementary MIS transistor as claimed in claim 1, wherein said insulating gate has oblique side walls at said first and second edges such that said insulating gate has a lateral size that decreases with increasing height away from a principal surface of said substrate.
Claim 6
Dependent Claim
63 words
A complementary MIS transistor as claimed in claim 1, wherein said N-type diffusion regions are formed by an ion implantation process conducted obliquely to a principal surface of said substrate while using said insulating gate as a mask, such that said N-type diffusion regions extend to a region of said substrate located immediately below said first and second edges of said insulating gate.
Claim 7
Dependent Claim
63 words
A complementary MIS transistor as claimed in claim 4, wherein said N-type diffusion regions are formed by an ion implantation process conducted obliquely to a principal surface of said substrate while using said insulating gate as a mask, such that said N-type diffusion regions extend to a region of said substrate located immediately below said first and second edges of said insulating gate.
Claim 8
Dependent Claim
17 words
A complementary MIS transistor as claimed in claim 1, wherein said insulating gate is doped to N-type.
Claim 9
Dependent Claim
17 words
A complementary MIS transistor as claimed in claim 2, wherein said insulating gate is doped to N-type.
Claim 10
Dependent Claim
17 words
A complementary MIS transistor as claimed in claim 4, wherein said insulating gate is doped to N-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-01 | 1998-01-31 | 1998-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-01 | 2002-01-31 | 2002-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-01 | 2006-01-31 | 2006-08-02 | $7700.00 | Window Closed / Lapsed |