High withstanding voltage MIS transistor

Claim 1

A high withstanding voltage MIS transistor with an offset gate structure comprising: a semiconductor substrate having a main surface and a region adjacent to said main surface, said region having a first conductivity type and having a first impurity concentration; source and drain regions formed in said region of said semiconductor substrate and having a second conductivity type; a first offset region formed in said region of said semiconductor substrate, connecting to said drain region, having a length of more than 1 micrometer, and having said second conductivity type, an impurity concentration of said first offset region being lower than an impurity concentration of said drain region, to substantially increase a drain region breakdown voltage; a first double offset region formed in said region of said semiconductor substrate with at least a portion of said first double offset region overlapping said first offset region, the double offset region having said first conductivity type and having a second impurity concentration to control said drain region breakdown voltage independent of said first impurity concentration of said region of said semiconductor substrate, said second impurity concentration being higher than said first impurity concentration so as to increase said impurity concentration of said first offset region; a gate insulating film formed on said main surface; and a gate electrode formed on said gate insulating film, and disposed between said source region and said first offset region, said first offset region being disposed between said gate electrode and said drain region.