Process for forming twin well CMOS integrated circuits

Claim 2

A complementary insulated gate field effect transistor comprising: a body of semiconductor material having an effectively planar surface, a first surface portion of which has formed therein a first region of a first conductivity type and a second surface portion of which has formed therein a second region of a second conductivity type; first and second thin gate insulator layers respectively formed on said first and second regions; a field insulator layer formed on a portion of said planar surface of said body between said first and second regions on which said first and second thin gate insulator layers are formed, said field insulator layer being effectively hardened against radiation such that said field insulator layer exhibits a flat-band voltage shift thereacross no greater than 20 volts over a total radiation dose range of at least 10 5 rads, and wherein said portion of said planar surface of said body on which said field insulator layer is formed is not lower than said first and second surface portions on which said first and second regions of said first and second conductivity types, respectively, are formed and on which said first and second thin gate insulator layers are respectively formed; first and second gates, having second and first conductivity types, respectively overlying said first and second thin gate insulator layers; source and drain regions of said second conductivity type formed in surface areas of said first region effectively aligned with sidewalls of said field insulator layer and said first gate; source and drain regions of said first conductivity type formed in surface areas of said second region effectively aligned with sidewalls of said field insulator layer and said second gate; and insulative spacers abutting sidewalls of said first and second gates and said field insulator layer and extending over portions of said source and drain regions.

Claim 3

A complementary insulated gate field effect transistor according to claim 1, wherein said field insulator layer comprises a laminated structure of a thermally grown insulator layer and a deposited insulator layer thereon.

Claim 4

A complementary insulated gate field effect transistor according to claim 2, wherein said body of semiconductor material comprises a silicon body and said laminated structure comprises a first layer of silicon dioxide thermally grown on said effectively planar surface of said silicon body and a second layer of chemically vapor deposited phosphosilicate glass atop said first layer of silicon dioxide.

Claim 5

A complementary insulated gate field effect transistor according to claim 2, wherein said first and second regions comprise first and second well regions, respectively, each of which has a retrograde impurity distribution profile therein.

Claim 6

A complementary insulated gate field effect transistor according to claim 3, wherein said first and second regions comprise first and second well regions, respectively, each of which has a retrograde impurity distribution profile therein.

Claim 7

A complementary insulated gate field effect transistor according to claim 3, wherein each of said first and second thin gate insulator layers comprises a silicon dioxide layer having a thickness on the order of "200-500 angstroms.

Claim 8

A complementary insulated gate field effect transistor according to claim 1, further comprising a layer of material of which said gates are made disposed on said field insulator layer between said first and second regions.

Claim 9

A complementary insulated gate field effect transistor according to claim 7, further including insulative spacers abutting sidewalls of said layer of material of which said gates are made and extending over portions of said field insulator layer.

Claim 10

A complementary insulated gate field effect transistor according to claim 8, wherein said first and second regions comprise first and second well regions, respectively, each of which has a retrograde impurity distribution profile therein.

Claim 11

A complementary insulated gate field effect transistor according to claim 1, further comprising: thin metal layers formed on each of said source and drain regions and said first and second gates; a further insulator layer selectively formed over said body and said field insulator layer exposing portions of said thin metal layers; and an interconnect metal layer overlying said further insulator layer and contacting exposed portions of said thin metal layers.

Claim 12

A complementary insulated gate field effect transistor according to claim 10, further comprising a layer of material of which said gates are made disposed on said field insulator layer between said first and second regions, another of said thin metal layers formed on said layer of material of which said gates are made, and wherein said interconnect metal layer interconnects each of the thin metal layers formed on said drain regions to the thin metal layer formed on said layer of material of which said gates are made.

Claim 13

A complementary insulated gate field effect transistor according to claim 11, wherein said interconnect metal layer includes respective thick metal plugs extending through apertures in said further insulator layer and contacting said thin metal layers exposed thereby, said thick metal plugs containing the metal of said thin metal layers.

Claim 14

A complementary insulated gate field effect transistor according to claim 12, further including insulative spacers abutting sidewalls of said layer of material of which said gates are made and extending over portions of said field insulator layer.

Claim 15

A complementary insulated gate field effect transistor according to claim 13, wherein said interconnect metal layer includes a thin transition metal layer contacting said metal plugs and a thick metal layer overlying said thin transition metal layer.

Claim 16

A complementary insulated gate field effect transistor according to claim 14, further including an additional insulator layer selectively formed over said interconnect metal layer exposing portions of said thick metal layer, and an additional interconnect metal layer and overlying said additional insulator layer and contacting exposed portions of said thick metal layer.

Claim 17

A complementary insulated gate field effect transistor accoridng to claim 10, wherein those portions of said source and drain regions beneath insulative spacers have a depth less than the depth of those portions of said source and drain regions beneath said thin metal layers.

Claim 18

A complementary insulated gate field effect transistor comprising; a body of semiconductor material in a first surface portion of which is formed a first well region of a first conductivity type and in a second surface portion of which is formed a second well region of a second conductivity type, each of said first and second well regions having a retrograde impurity distribution profile therein; a field insulator layer formed on said body exposing said first and second well regions; first and second thin gate insulator layers respectively formed on said first and second well regions; first and second gates, having second and first conductivity types, respectively, overlying said first and second gate insulator layers; source and drain regions of said second conductivity type formed in the surface areas of said first well region between said field insulator layer and said first gate; source and drain regions of said first conductivity type formed in the surface area of said second well region between said field insulator and said second gate; insulative spacers abutting sidewalls of said first and second gates and extending over portions of said source and drain regions; thin metal layers formed on each of said source and drain regions and said first and second gates; a further insulator layer selectively formed over said body and said field insulator layer exposing portions of said thin metal layers; an interconnect metal layer overlying said further insulator layer and contacting exposed portions of said thin metal layers; and a layer of material of which said gates are made disposed on said field insulator layer between said first and second regions, another of said thin metal layers formed on said layer of material of which the gates are made, and wherein said interconnect metal layer connects each of the thin metal layers formed on said drain regions to the thin metal layer formed on said layer of material of which the gates are made.

Claim 19

A complementary insulated gate field effect transistor comprising; a body of semiconductor material in a first surface portion of which is formed a first well region of a first conductivity type and in a second surface portion of which is formed a second well region of a second conductivity type, each of said first and second well regions having a retrograde impurity distribution profile therein; a field insulator layer formed on said body exposing said first and second well regions; first and second thin gate insulator layers respectively formed on said first and second well regions; first and second gates, having second and first conductivity types, respectively, overlying said first and second gate insulator layers; source and drain regions of said second conductivity type formed in the surface areas of said first well region between said field insulator layer and said first gate; source and drain regions of said first conductivity type formed in the surface area of said second well region between said field insulator and said second gate; insulative spacers abutting sidewalls of said first and second gates and extending over portions of said source and drain regions; thin metal layers formed on each of said source and drain regions and said first and second gates; a further insulator layer selectively formed over said body and said field insulator layer exposing portions of said thin metal layers; an interconnect metal layer overlying said further insulator layer and contacting exposed portions of said thin metal layers; and a layer of material of which said gates are made disposed on said field insulator layer between said first and second regions, another of said thin metal layers formed on said layer of material of which the gates are made, and wherein said interconnect metal layer connects each of the thin metal layers formed on said drain regions to the thin metal layer formed on said layer of material of which the gates are made.

Claim 20

A complementary insulated gate field effect transistor according to claim 17, wherein said interconnect metal layer includes respective thick metal plugs extending through apertures in said further insulator layer and contacting said thin metal layers exposed thereby, said thick metal plugs containing the metal of said thin metal layers.

Claim 21

A complementary insulated gate field effect transistor according to claim 18, further including insulator spacers abutting sidewalls of said layer of material of which said gates are made and extending over the surface of said field insulator layer.

Claim 22

A complementary insulated gate field effect transistor according to claim 19, wherein said interconnect metal layer includes a thin transition metal layer contacting said metal plugs and a thick metal layer overlying said thin transition metal layer.

Claim 23

A complementary insulated gate field effect transistor according to claim 20, further including an additional insulator layer selectively formed over said interconnect metal layer exposing portions of said thick metal layer, and an additional interconnect metal layer overlying said additional insulator layer and contacting exposed portions of said thick metal layer.

Claim 24

A complementary insulated gate field effect transistor comprising: a body of semiconductor material in a first surface portion of which is formed a first well region of a first conductivity type and in a second surface portion of which is formed a second well region of a second conductivity type, each of said first and second well regions having a retrograde impurity distribution profile therein; a field insulator layer formed on said body exposing said first and second well regions; first and second thin gate insulator layers respectively formed on said first and second well regions; first and second gates, having second and first conductivity types, respectively, overlying said first and second gate insulator layers; source and drain regions of said second conductivity type formed in the surface areas of said first well region between said field insulator layer and said first gate; source and drain regions of said first conductivity type formed in the surface areas of said second well region between said field insulator layer and said second gate; insulative spacers abutting sidewalls of said first and second gates and extending over portions of said source and drain regions; thin metal layers formed on each of said source and drain regions and said first and second gates; a further insulator layer selectively formed over said body and said field insulator layer exposing portions of said thin metal layers; and an interconnect metal layer overlying said further insulator layer and contacting exposed portions of said thin metal layers; and wherein those portions of said source and drain regions beneath insulative spacers have a depth less than the depth of those portions of said source and drain regions beneath said thin metal layers.

Claim 25

A complementary insulated gate field effect transistor comprising: a body of semiconductor material in a first surface portion of which is formed a first well region of a first conductivity type and in a second surface portion of which is formed a second well region of a second conductivity type, each of said first and second well regions having a retrograde impurity distribution profile therein; a field insulator layer formed on said body exposing said first and second well regions; first and second thin gate insulator layers respectively formed on said first and second well regions; first and second gates, having second and first conductivity types, respectively, overlying said first and second gate insulator layers; source and drain regions of said second conductivity type formed in the surface areas of said first well region between said field insulator layer and said first gate; source and drain regions of said first conductivity type formed in the surface areas of said second well region between said field insulator layer and said second gate; insulative spacers abutting sidewalls of said first and second gates and extending over portions of said source and drain regions; thin metal layers formed on each of said source and drain regions and said first and second gates; a further insulator layer selectively formed over said body and said field insulator layer exposing portions of said thin metal layers; and an interconnect metal layer overlying said further insulator layer and contacting exposed portions of said thin metal layers; and wherein those portions of said source and drain regions beneath insulative spacers have a depth less than the depth of those portions of said source and drain regions beneath said thin metal layers.