Multiple tilted angle ion implantation MOSFET method

Claim 1

A method for fabricating a lightly doped drain MOSFET integrated circuit device having reduced source/drain series resistance for increased saturation current comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer; forming a pattern of lightly and successively more heavily doped regions in said substrate under said structures by multiple ion implantations wherein said multiple ion implantations are at least three different angles of successive greater amount from the vertical, the dosage of said implantations is between about 1 E 12 to 5 E 13 atoms/cm 2 and the acceleration potential of said implantations is between about 50 to 80 Kev; annealing said lightly and successively more heavily doped regions at a temperature and time to cause dopant diffusion between said lightly doped to more heavily doped regions; forming a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; and forming a pattern of heavily doped regions in said substrate contiguous with said more heavily doped region adjacent to said dielectric spacer structure which is on the sidewalls of said structures and over the adjacent portions of said substrate.

Claim 2

A method for fabricating a lightly doped drain MOSFET integrated circuit device having reduced source/drain series resistance for increased saturation current comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer; forming a pattern of lightly and successively more heavily doped regions in said substrate under said structures by multiple ion implantations wherein said multiple ion implantations are at least three different angles of successive greater amount from the vertical, the dosage of said implantations is between about 1 E 12 to 5 E 13 atoms/cm 2 and the acceleration potential of said implantations is between about 50 to 80 Kev; annealing said lightly and successively more heavily doped regions at a temperature and time to cause dopant diffusion between said lightly doped to more heavily doped regions; forming a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; and forming a pattern of heavily doped regions in said substrate contiguous with said more heavily doped region adjacent to said dielectric spacer structure which is on the sidewalls of said structures and over the adjacent portions of said substrate.

Claim 9

A method for fabricating a lightly doped drain MOSFET integrated circuit device having reduced source/drain series resistance for increased saturation current comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer; forming a pattern of lightly and successively more heavily doped regions in said substrate under said structures by multiple ion implantations wherein said multiple ion implantations are at least three different angles of successive greater amount from the vertical, the dosage of said multiple implantations is between about 1 E 12 to 5 E 13 atoms/cm 2 and the acceleration power of said multiple implantations is between about 50 to 80 Kev; annealing said lightly and successively more heavily doped regions at a temperature and time to cause dopant diffusion forming regions consisting of doping concentrations gradually varying from a lightly doped concentration of about 1 E 17 atoms/cm 3 to about 5 E 17 atoms/cm 3 to about 1 E 18 atoms/cm 3 to a more heavily doped concentration of about 1 E 18 atoms/cm 3 ; forming a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; forming a pattern of heavily doped regions in said substrate contiguous with said more heavily doped region adjacent to said dielectric spacer structure which is on the sidewalls of said structures and over the adjacent portions of said substrate.

Claim 10

A method for fabricating a lightly doped drain MOSFET integrated circuit device having reduced source/drain series resistance for increased saturation current comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer; forming a pattern of lightly and successively more heavily doped regions in said substrate under said structures by multiple ion implantations wherein said multiple ion implantations are at least three different angles of successive greater amount from the vertical, the dosage of said multiple implantations is between about 1 E 12 to 5 E 13 atoms/cm 2 and the acceleration power of said multiple implantations is between about 50 to 80 Kev; annealing said lightly and successively more heavily doped regions at a temperature and time to cause dopant diffusion forming regions consisting of doping concentrations gradually varying from a lightly doped concentration of about 1 E 17 atoms/cm 3 to about 5 E 17 atoms/cm 3 to about 1 E 18 atoms/cm 3 to a more heavily doped concentration of about 1 E 18 atoms/cm 3 ; forming a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; forming a pattern of heavily doped regions in said substrate contiguous with said more heavily doped region adjacent to said dielectric spacer structure which is on the sidewalls of said structures and over the adjacent portions of said substrate.

Claim 11

A method for fabricating a lightly doped drain MOSFET integrated circuit device having reduced source/drain series resistance for increased saturation current comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer; forming a pattern of lightly and successively more heavily doped regions in said substrate under said structures by multiple ion implantations wherein said multiple ion implantations are at least five different angles of successive greater amount from the vertical, the dosage of said multiple implantations is between about 1 E 12 to 5 E 13 atoms/cm 2 and the acceleration potential of said implantations is between about 50 to 80 Kev.; annealing said lightly and successively more heavily doped regions at a temperature and time to cause dopant diffusion, between said lightly doped to more heavily doped regions so that as a result of said annealing and said multiple ion implantations there is a gradual reduced concentration as said lightly doped regions extend under said gate electrode structures is created; forming a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; and forming a pattern of heavily doped regions in said substrate contiguous with said more heavily doped region adjacent to said dielectric spacer structure which is on the sidewalls of said structures and over the adjacent portions of said substrate.

Claim 12

A method for fabricating a lightly doped drain MOSFET integrated circuit device having reduced source/drain series resistance for increased saturation current comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide and a polysilicon layer; forming a pattern of lightly and successively more heavily doped regions in said substrate under said structures by multiple ion implantations wherein said multiple ion implantations are at least five different angles of successive greater amount from the vertical, the dosage of said multiple implantations is between about 1 E 12 to 5 E 13 atoms/cm 2 and the acceleration potential of said implantations is between about 50 to 80 Kev.; annealing said lightly and successively more heavily doped regions at a temperature and time to cause dopant diffusion, between said lightly doped to more heavily doped regions so that as a result of said annealing and said multiple ion implantations there is a gradual reduced concentration as said lightly doped regions extend under said gate electrode structures is created; forming a dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; and forming a pattern of heavily doped regions in said substrate contiguous with said more heavily doped region adjacent to said dielectric spacer structure which is on the sidewalls of said structures and over the adjacent portions of said substrate.