US5147811A
Expired / Lapsed
US
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Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the source/drain regions
Assignee: Toshiba Corp
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Filing: 1991-03-11
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Granted: 1992-09-15
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Expires: 2011-03-11
Abstract
Abstract The invention provides a novel method of manufacturing a semiconductor device comprising those sequential steps including the following, formation of a floating gate electrode on a region predetermined for the formation of the first conductive channel across an insulation film, followed by superimposition of a control gate electrode on the floating gate electrode across another insulation film. After completing the formation of the stacked gate electrode unit, the first conductive impurities are injected into silicon substrate by applying a minimum of 8 degrees of angle against the normal of this substrate under aid of ionic injection, and then forms a region containing strong density of the first conductive impurities adjacent to the boundary of a layer of diffused second conductive impurities which is at least predetermined to become the drain region of the transistor incorporating the stacked gate electrode unit. As a result of the provision of the region containing strong density of impurities injected in the oblique direction, the efficiency in the writing of data into the floating gate electrode is significantly promoted, and at the same time occurrence of "short-channel" effect can securely be suppressed as well.
Inventors
- 👤 Eiji Sakagami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:52
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; H10B; H10B69/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
244 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor element region on a semiconductor substrate; forming a first insulation layer on a resulting semiconductor structure; forming a first conductive layer on said first insulation layer; forming a second insulation layer on said first conductive layer; forming a second conductive layer on said second insulation layer; patterning said insulation and conductive layers to form a floating gate electrode and a control gate electrode; selectively injecting ions of an impurity having a first conductivity type into said element region at an angle of at least 8° relative to a normal of an upper surface of said element region; selectively injecting ions of an impurity having a second conductivity type into said element region; and activating said impurities of the second conductivity type to form a source region and a drain region and a said impurities of the first conductivity type to form a pocket region adjacent to an edge of said drain region, wherein the step of injecting ions having an impurity of the first conductivity type is governed by the expression X.sub.p ·tanθ≧X.sub.jl where X p designates a mean projected range of the ions injected into said element region, θ designates the angle at which the ions are injected relative to the normal of the upper surface of said element region, and X jl designates a distance that the edge of said drain region extends under said floating gate electrode.
Claim 2
Independent Claim
244 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor element region on a semiconductor substrate; forming a first insulation layer on a resulting semiconductor structure; forming a first conductive layer on said first insulation layer; forming a second insulation layer on said first conductive layer; forming a second conductive layer on said second insulation layer; patterning said insulation and conductive layers to form a floating gate electrode and a control gate electrode; selectively injecting ions of an impurity having a first conductivity type into said element region at an angle of at least 8° relative to a normal of an upper surface of said element region; selectively injecting ions of an impurity having a second conductivity type into said element region; and activating said impurities of the second conductivity type to form a source region and a drain region and a said impurities of the first conductivity type to form a pocket region adjacent to an edge of said drain region, wherein the step of injecting ions having an impurity of the first conductivity type is governed by the expression X.sub.p ·tanθ≧X.sub.jl where X p designates a mean projected range of the ions injected into said element region, θ designates the angle at which the ions are injected relative to the normal of the upper surface of said element region, and X jl designates a distance that the edge of said drain region extends under said floating gate electrode.
Claim 3
Independent Claim
239 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor element region on a semiconductor substrate; forming a first insulation layer on a resulting semiconductor structure; forming a first conductive layer on said first insulation layer; forming a second insulation layer on said first conductive layer; forming a second conductive layer on said second insulation layer; patterning said insulation and conductive layers to form a floating gate electrode and a control gate electrode; selectively injecting ions of an impurity having a first conductivity type into said element region at an angle of at least 8° relative to a normal of said an upper surface of said element region; selectively injecting ions of an impurity having a second conductivity type into said element region; and activating said impurities of the second conductivity type to form a source region and a drain region and a said impurities of the first conductivity type to form a pocket region adjacent to an edge of said drain region, wherein the step of injecting ions having an impurity of the first conductivity type is governed by the expression 1/2X.sub.j ≦X.sub.p ≦2X.sub.j where X p designate a mean projected range of the ions injected into said element region, θdesignates the angle at which the ions are injected relative to the normal of the upper surface of said element region, and X j designates a depth of a junction of said drain region.
Claim 4
Independent Claim
239 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor element region on a semiconductor substrate; forming a first insulation layer on a resulting semiconductor structure; forming a first conductive layer on said first insulation layer; forming a second insulation layer on said first conductive layer; forming a second conductive layer on said second insulation layer; patterning said insulation and conductive layers to form a floating gate electrode and a control gate electrode; selectively injecting ions of an impurity having a first conductivity type into said element region at an angle of at least 8° relative to a normal of said an upper surface of said element region; selectively injecting ions of an impurity having a second conductivity type into said element region; and activating said impurities of the second conductivity type to form a source region and a drain region and a said impurities of the first conductivity type to form a pocket region adjacent to an edge of said drain region, wherein the step of injecting ions having an impurity of the first conductivity type is governed by the expression 1/2X.sub.j ≦X.sub.p ≦2X.sub.j where X p designate a mean projected range of the ions injected into said element region, θdesignates the angle at which the ions are injected relative to the normal of the upper surface of said element region, and X j designates a depth of a junction of said drain region.
Claim 5
Dependent Claim
73 words
The method according to claim 1 or 2, wherein the step of activating comprises a step of activating said impurities of the first conductivity type to form a second pocket region adjacent to an edge of said source region, where X j further designates a depth of a junction of said source region and X jl further designates a distance that the edge of said source region extends under said floating gate electrode.
Claim 6
Dependent Claim
65 words
The method of manufacturing the semiconductor device according to claim 1 or 2, further comprising a step of adjusting a density of said impurities of the first conductivity type injected into said pocket region to be greater than a density of impurities present in a center of the channel region of said device and less than impurities present in the drain region of said device.
Claim 7
Dependent Claim
39 words
The method of manufacturing the semiconductor device according to claim 1 or 2, wherein said step of injecting ions of the impurity having the first conductivity type into said element region is executed while continuously rotating said semiconductor substrate.
Claim 8
Dependent Claim
38 words
The method of manufacturing the semiconductor device according to claim 1 or 2, wherein said step of injecting ions of the impurity having the first conductivity type into said element region is executed while intermittently rotating said substrate.
Claim 9
Dependent Claim
53 words
The method of manufacturing the semiconductor device according to claim 1 or 2, wherein said step of injecting ions of the impurity having the first conductivity type into said element region is executed at a maximum angle of sixty (60) degrees relative to the normal of the upper surface of said element region.
Claim 10
Dependent Claim
82 words
The method of manufacturing the semiconductor device according to claim 1 or 2, wherein the step of injecting ions of the impurity having the first conductivity type into said element region executed by applying a minimum of eight degrees of angle relative to the normal of the upper surface of said element region is executed simultaneously with the step of injection ions of the impurity of the second conductivity type for the formation of the source and drain regions of said device.
References Cited (Backward Citations)
US4232439A
Cited
JPS57130475A
Cited
JPS5893279A
Cited
JPS5961185A
Cited
US4771012A
Cited
EP0333583A2
Cited
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