Patent US2595986A successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0333583A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method of producing a semiconductor device

Assignee: Fujitsu Ltd
•
Filing: 1989-03-14
•
Granted: —
•
Expires: 2009-03-14
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of producing a semiconductor device comprises the steps of : preparing a semiconductor substrate (1), forming a gate insulating layer on the semiconductor substrate, forming a gate electrode (4) on the gate insulating layer, forming a source/drain region (2,3) in the semiconductor substrate, forming a cover layer (10,11) on the entire exposed surface, forming a mask (12) on the cover layer having an opening over the gate electrode (4), implanting one conductivity type impurity ions into the semiconductor substrate (1) through the cover layer, the gate electrode and the gate insulating layer as the first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate therethrough as the second implanting process, at an implanting angle larger than that used in the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as the first ion implanting process, and at a dosage smaller than that in the first ion implanting process, whereby the one conductivity type impurity ions are compensated at laterally spread portions.

Inventors

  • 👤 Haruhisa Mori

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 04:40
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; H10P; H10P30/00; H10P30/20; H10P30/22

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 175 words
A method of producing a semiconductor device comprising the steps of: preparing a semiconductor substrate (1), forming a gate insulating (5) layer on the semiconductor substrate, forming a gate electrode (4) on the gate insulating layer, forming a source/drain region (2,3) in the semiconductor substrate, forming a cover layer (10,11) on the entire exposed surface, forming a mask (12) on the cover layer having an opening over the gate electrode, implanting one conductivity type impurity ions into the semiconductor substrate through the cover layer, the gate electrode and the gate insulating layer as the first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate there­through as the second implanting process at an implanting angle larger than that of the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as in the first ion implanting process and at a dosage smaller than in the first ion implanting process, whereby said one conductivity type impurity ions are compensated at laterally spread portions.
Claim 2
Independent Claim 175 words
A method of producing a semiconductor device comprising the steps of: preparing a semiconductor substrate (1), forming a gate insulating (5) layer on the semiconductor substrate, forming a gate electrode (4) on the gate insulating layer, forming a source/drain region (2,3) in the semiconductor substrate, forming a cover layer (10,11) on the entire exposed surface, forming a mask (12) on the cover layer having an opening over the gate electrode, implanting one conductivity type impurity ions into the semiconductor substrate through the cover layer, the gate electrode and the gate insulating layer as the first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate there­through as the second implanting process at an implanting angle larger than that of the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as in the first ion implanting process and at a dosage smaller than in the first ion implanting process, whereby said one conductivity type impurity ions are compensated at laterally spread portions.
Claim 3
Dependent Claim 17 words
A method according to claim 1, wherein said semiconductor substrate (1) is a p type silicon substrate.
Claim 4
Dependent Claim 23 words
A method according to claim 1, wherein said gate electrode (4) is a polycristalline silicon electrode having a thickness of about 4000 Å.
Claim 5
Dependent Claim 31 words
A method according to claim 1, wherein said insulating layer (10,11) positioned on the entire exposed surface is composed of two phospho-silicate glass layers having a total thickness of 1.1 µm.
Claim 6
Dependent Claim 18 words
A method according to claim 1, wherein said one conductivity type impurity ions are n type impurity ions.
Claim 7
Dependent Claim 16 words
A method according to claim 5, wherein said n type impurity ions are phosphorus ions (P⁺)
Claim 8
Dependent Claim 33 words
A method according to claim 1, wherein said one conductivity type impurity ions are implanted at an implanting angle of 0 to 7° with respect to the normal plane of the semiconductor device.
Claim 9
Dependent Claim 33 words
A method according to claim 1, wherein said one conductivity type impurity ions are implanted at a projective range of 0.5 to 3 µm and a dosage of 1 to 5 x 10¹³/cm².
Claim 10
Dependent Claim 18 words
A method according to claim 1, wherein said opposite conductivity type impurity ions are p type impurity ions.
Claim 11
Dependent Claim 16 words
A method according to claim 9, wherein said p type impurity ions are boron ions (B⁺).
Claim 12
Dependent Claim 33 words
A method according to claim 1, wherein said opposite conductivity type impurity ions are implanted at an implanting angle of larger than 7° with respect to the normal plane of the semiconductor device.
Claim 13
Dependent Claim 33 words
A method according to claim 1, wherein said opposite conductivity type impurity ions are implanted at a projective range of 0.5 to 3 µm and a dosage of 1 to 5 x 10¹²/cm².

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag