EP0506089B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Static random access type semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1992-03-27
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Granted: 1997-11-19
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Expires: 2012-03-27
Abstract
No abstract record available.
Inventors
- 👤 Hirotada c/o Mitsubishi Denki K.K. LSI Kuriyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:09
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6729; H10D30/673; H10D30/6733
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
156 words
A semiconductor memory device including a memory cell constituted by a pair of thin film driver transistors (Q 1 , Q 2 ) of a first conductivity type and a pair of thin film load transistors (Q 5 , Q 6 ) of a second conductivity type making up a flipflop circuit, and a pair of thin film access transistors (Q 3 , Q 4 ), comprising: a semiconductor substrate (32) having a main surface; an insulating layer (33a) formed on said main surface of the semiconductor substrate; a first group consisting of at least one of said thin film transistors (1 to 12) and arranged on said insulating layer (33a). an interlayer insulating layer (33b) covering the surface of said first group of thin film transistors (1-12); and a second group consisting of the remainder of said thin film transistors (11 to 17) of said memory cell and arranged on said interlayer insulating layer (33b).
Claim 2
Dependent Claim
54 words
The semiconductor memory device according to claim 1, wherein said first group of thin film transistors includes said driver transistors (Q 1 , Q 2 ) and said access transistors (Q 3 , Q 4 ) and said second group of thin film transistors includes said load transistors (Q 5 , Q 6 ).
Claim 3
Dependent Claim
75 words
The semiconductor memory device according to claims 1 or 2, wherein each transistor in said first group of thin film transistors includes a pair of impurity regions (1, 3, 5, 6, 8) formed in a first semiconductor layer on said insulating layer (33a) and each transistor in said second group of thin film transistors includes a pair of impurity regions (13, 15, 17) formed in a second semiconductor layer on said interlayer insulating layer (33b).
Claim 4
Dependent Claim
101 words
The semiconductor memory device according to claim 3, wherein a gate electrode of said driver transistor (Q 1 , Q 2 ) included in said first group of thin film transistors and gate electrode of said load transistor (Q 5 , Q 6 ) included in said second group of thin film transistors are formed of a common layer (11, 12), and said first semiconductor layer included in said first group of thin film transistors and said second semiconductor layer included in said second group of thin film transistors are arranged opposing each other with said common layer (11,12) interposed therebetween.
References Cited (Backward Citations)
No citation records indexed.
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