Semiconductor device having reduced leakage current

Claim 2

A thin film insulated gate semiconductor device comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on said buffer film; a semiconductor layer extending between said source and drain semiconductor regions; and a gate electrode provided over said semiconductor layer with a gate insulating layer therebetween; and wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region provided under and in contact with the first region, the first region comprises a crystalline structure and the second region comprises an amorphous structure, and wherein at least said first region of said semiconductor layer extends beyond side edges of said gate electrode and wherein the second region has a conductivity type opposite to that of said source and drain regions and the first region is substantially intrinsic.

Claim 3

The device of claim 1 wherein the first region has a single-crystalline structure.

Claim 4

The device of claim 2 wherein the first region is a channel forming region.

Claim 5

The device of claim 1 wherein the second region has a larger band gap than the first region.

Claim 6

The device of claim 1 wherein the first region comprises silicon.

Claim 7

The device of claim 1 wherein said semiconductor layer and said source and drain regions have substantially the same thickness.

Claim 8

The device of claim 1 wherein thickness of said source and drain regions is larger than thickness of said first region.

Claim 9

An insulated gate thin film semiconductor device comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on said buffer film; a semiconductor layer extending between said source and drain semiconductor regions; a gate insulating layer contacting said semiconductor layer; and a gate electrode located adjacent to said semiconductor layer with said gate insulating layer therebetween, wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region provided under and in contact with the first region and wherein said first region comprises a single-crystalline silicon while said second region comprises amorphous silicon doped with carbon, nitrogen, oxygen or a combination thereof, said second region having a lower crystallinity than said first region and wherein the concentration of said carbon, nitrogen and oxygen in said second region is 8×10 9 cm -3 or more.

Claim 10

An insulated gate thin film semiconductor device comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on said buffer film; a semiconductor layer extending between said source and drain semiconductor regions; a gate insulating layer contacting said semiconductor layer; and a gate electrode located adjacent to said semiconductor layer with said gate insulating layer therebetween, wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region provided under and in contact with the first region and wherein said first region comprises a single-crystalline silicon while said second region comprises amorphous silicon doped with carbon, nitrogen, oxygen or a combination thereof, said second region having a lower crystallinity than said first region and wherein the concentration of said carbon, nitrogen and oxygen in said second region is 8×10 9 cm -3 or more.

Claim 11

The device of claim 5 wherein the second region has a lower mobility than said first region.

Claim 12

The device of claim 1 wherein the second region has a smaller mobility than the first region.

Claim 13

The device of claim 8 wherein concentration of each of carbon, oxygen and nitrogen in the first region is 7×10 19 cm -3 or less.

Claim 14

An insulated gate thin film transistor comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer comprising silicon, provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film provided on said semiconductor layer; and a gate electrode provided over said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region provided between said first region and said buffer film, the first region has a crystalline structure and the second region has an amorphous structure, and at least said first region of the semiconductor layer extending beyond side edges of said gate electrode to form an offset region therein; and wherein only the second region of said semiconductor layer is intentionally doped with carbon, nitrogen, oxygen or a combination thereof.

Claim 15

An insulated gate thin film transistor comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer comprising silicon, provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film provided on said semiconductor layer; and a gate electrode provided over said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region provided between said first region and said buffer film, the first region has a crystalline structure and the second region has an amorphous structure, and at least said first region of the semiconductor layer extending beyond side edges of said gate electrode to form an offset region therein; and wherein only the second region of said semiconductor layer is intentionally doped with carbon, nitrogen, oxygen or a combination thereof.

Claim 16

The thin film transistor of claim 12 wherein the concentration of at least one of said carbon, nitrogen and oxygen in said second region is 8×10 19 cm -3 or more.

Claim 17

The thin film transistor of claim 13 wherein a concentration of each of carbon, oxygen and nitrogen in the first region is 7×10 19 atoms/cm 3 or less.

Claim 18

An insulated gate thin film transistor comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film provided on said semiconductor layer; and a gate electrode provided over said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a crystalline structure and the second region has an amorphous structure, and at least said first region of the semiconductor layer extending beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a lower energy band gap than said second region and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 19

An insulated gate thin film transistor comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film provided on said semiconductor layer; and a gate electrode provided over said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a crystalline structure and the second region has an amorphous structure, and at least said first region of the semiconductor layer extending beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a lower energy band gap than said second region and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 20

An insulated gate thin film transistor comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film contacting said semiconductor layer; and a gate electrode provided over said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a crystalline structure and the second region has an amorphous structure, and at least said first region of said semiconductor layer extending beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a larger carrier mobility than said second region and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 21

An insulated gate thin film transistor comprising: a substrate; a buffer film formed on said substrate; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film contacting said semiconductor layer; and a gate electrode provided over said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a crystalline structure and the second region has an amorphous structure, and at least said first region of said semiconductor layer extending beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a larger carrier mobility than said second region and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 22

The thin film transistor of claim 12 wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 23

The insulated gate thin film semiconductor device of claim 1 wherein said buffer film comprises silicon oxide.

Claim 24

A thin film insulated gate semiconductor device comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on said insulating surface; a semiconductor layer extending between said source and drain semiconductor regions; and a gate electrode adjacent to said semiconductor layer with a gate insulating layer therebetween; and wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region distant from said gate insulating layer, the first region having a higher crystallinity than said second region, and wherein at least said first region of said semiconductor layer extends beyond side edges of said gate electrode, and wherein the second region has a conductivity type opposite to that of said source and drain regions, and the first region is substantially intrinsic.

Claim 25

A thin film insulated gate semiconductor device comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on said insulating surface; a semiconductor layer extending between said source and drain semiconductor regions; and a gate electrode adjacent to said semiconductor layer with a gate insulating layer therebetween; and wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region distant from said gate insulating layer, the first region having a higher crystallinity than said second region, and wherein at least said first region of said semiconductor layer extends beyond side edges of said gate electrode, and wherein the second region has a conductivity type opposite to that of said source and drain regions, and the first region is substantially intrinsic.

Claim 26

An insulated gate thin film semiconductor device comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on said insulating surface; a semiconductor layer extending between said source and drain semiconductor regions; a gate insulating layer contacting said semiconductor layer; and a gate electrode located adjacent to said semiconductor layer with said gate insulating layer therebetween, wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region distant from said gate insulating layer, and wherein said first region comprises a single-crystalline silicon while said second region comprises amorphous silicon doped with carbon, nitrogen, oxygen or a combination thereof, said second region having a low crystallinity than said first region, and wherein the concentration of said carbon, nitrogen and oxygen in said second region is 8×10 19 cm - or more.

Claim 27

An insulated gate thin film semiconductor device comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on said insulating surface; a semiconductor layer extending between said source and drain semiconductor regions; a gate insulating layer contacting said semiconductor layer; and a gate electrode located adjacent to said semiconductor layer with said gate insulating layer therebetween, wherein said semiconductor layer includes a first region contacting said gate insulating layer and a second region distant from said gate insulating layer, and wherein said first region comprises a single-crystalline silicon while said second region comprises amorphous silicon doped with carbon, nitrogen, oxygen or a combination thereof, said second region having a low crystallinity than said first region, and wherein the concentration of said carbon, nitrogen and oxygen in said second region is 8×10 19 cm - or more.

Claim 28

An insulated gate thin film transistor comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer comprising silicon, provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film adjacent to said semiconductor layer; and a gate electrode adjacent to said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region distant from said gate insulating film, the first region has a higher crystallinity than said second region, and at least said first region of the semiconductor layer extends beyond side edges of said gate electrode to form an offset region therein; and wherein only the second region of said semiconductor layer is intentionally doped with carbon, nitrogen, oxygen or a combination thereof.

Claim 29

An insulated gate thin film transistor comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate on said buffer film; a semiconductor layer comprising silicon, provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film adjacent to said semiconductor layer; and a gate electrode adjacent to said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region distant from said gate insulating film, the first region has a higher crystallinity than said second region, and at least said first region of the semiconductor layer extends beyond side edges of said gate electrode to form an offset region therein; and wherein only the second region of said semiconductor layer is intentionally doped with carbon, nitrogen, oxygen or a combination thereof.

Claim 30

An insulated gate thin film transistor comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film adjacent to said semiconductor layer; and a gate electrode adjacent to said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a higher crystallinity than the second region, and at least said first region of the semiconductor layer extends beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a lower energy band gap than said second region, and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 31

An insulated gate thin film transistor comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film adjacent to said semiconductor layer; and a gate electrode adjacent to said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a higher crystallinity than the second region, and at least said first region of the semiconductor layer extends beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a lower energy band gap than said second region, and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 32

An insulated gate thin film transistor comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film contacting said semiconductor layer; and a gate electrode adjacent to said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a higher crystallinity than said second region, and at least said first region of said semiconductor layer extends beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a larger carrier mobility than said second region, and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.

Claim 33

An insulated gate thin film transistor comprising: a substrate having an insulating surface; a pair of source and drain semiconductor regions containing hydrogen therein provided on the surface of said substrate; a semiconductor layer provided on the surface of said substrate and extending between said source and drain semiconductor regions; a gate insulating film contacting said semiconductor layer; and a gate electrode adjacent to said semiconductor layer with said gate insulating film therebetween; wherein said semiconductor layer includes a first region contacting said gate insulating film and a second region located between said first region and said surface of the substrate, the first region has a higher crystallinity than said second region, and at least said first region of said semiconductor layer extends beyond side edges of said gate electrode to form an offset region therein; and wherein said first region has a larger carrier mobility than said second region, and wherein said gate electrode is provided with an oxide formed by oxidizing a surface thereof and said source and drain regions are aligned with edges of said oxide.