US5275872A
Expired / Lapsed
US
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Polycrystalline silicon thin film transistor
Assignee: Industrial Technology Research Institute
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Filing: 1991-08-08
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Granted: 1994-01-04
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Expires: 2011-08-08
Abstract
Abstract An improved field effect transistor having a source region, a drain region, and channel region in a polycrystalline silicon layer, the improvement being that the polycrystalline silicon layer has approximately equal concentrations of N and P type dopants embodied therein, which serves to restrain movement of P/N junctions.
Inventors
- 👤 Kun-Zen Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10P; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/15; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24926; Y10T428/26; Y10T428/263; Y10T428/264; Y10T428/265
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
140 words
A field effect transistor having a source region, a drain region, and a channel region in a polycrystalline silicon layer supported on an insulating substrate of a material selected from the group consisting of silicon, glass, quartz, sapphire, ceramic, and aluminum oxide; said entire polycrystalline silicon layer having a thickness in the range of 500 to 5000 Angstroms and, having embodied therein approximately equal concentrations of P and N type dopants that are uniformly distributed, said dopants each being present in a concentration in the range of 1×10 16 to 1×10 20 atoms/cm 3 , and spaced apart source and drain regions in said polycrystalline silicon layer defining a channel region there between, the resultant modified polycrystalline silicon layer effectively limiting the lateral diffusion of the dopants forming the source and drain regions thereby providing a stable channel region length.
Claim 2
Dependent Claim
140 words
A field effect transistor having a source region, a drain region, and a channel region in a polycrystalline silicon layer supported on an insulating substrate of a material selected from the group consisting of silicon, glass, quartz, sapphire, ceramic, and aluminum oxide; said entire polycrystalline silicon layer having a thickness in the range of 500 to 5000 Angstroms and, having embodied therein approximately equal concentrations of P and N type dopants that are uniformly distributed, said dopants each being present in a concentration in the range of 1×10 16 to 1×10 20 atoms/cm 3 , and spaced apart source and drain regions in said polycrystalline silicon layer defining a channel region there between, the resultant modified polycrystalline silicon layer effectively limiting the lateral diffusion of the dopants forming the source and drain regions thereby providing a stable channel region length.
Claim 3
Dependent Claim
34 words
The semiconductor device of claim 1 wherein said polycrystalline silicon layer has a thickness in the range of 500 to 1000 Angstroms and a grain size in the range of 0.05 to 1.0 micrometers.
Claim 4
Dependent Claim
34 words
The semiconductor device of claim 2 wherein said P and N type impurities are phosphorus and boron respectively, each in a concentration in the range of 1×10 16 to 1×10 20 cm -3 .
Claim 5
Dependent Claim
26 words
The semiconductor device of claim 3 wherein the concentrations of phosphorous and boron are in the range of 5×10 18 to 5×10 19 cm -3 .
Claim 6
Dependent Claim
14 words
The field effect transistor of claim 4 wherein said polycrystalline silicon layer is hydrogenated.
Claim 7
Dependent Claim
22 words
The field effect transistor of claim 2 wherein said substrate is a monocrystalline silicon body with an overlying layer of silicon dioxide.
Claim 8
Dependent Claim
20 words
The field effect transistor of claim 2 wherein said channel width is in the range of 0.5 to 20 micrometers.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-01-03 | 1997-07-05 | 1998-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-03 | 2001-07-05 | 2002-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-03 | 2005-07-05 | 2006-01-04 | $7700.00 | Window Closed / Lapsed |