Patent JPS5612341A successfully refreshed from Google Patents.
US5801416A
Expired / Lapsed
US
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FET having gate insulating film of nonuniform thickness and asymmetrical source and drain structures
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-01-24
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Granted: 1998-09-01
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Expires: 2016-01-24
Abstract
Abstract A high withstand voltage transistor and a method for manufacturing the same are disclosed. The transistor includes a semiconductor substrate, a field oxide film, a channel region formed of first and second channel regions each having a different concentration level, a gate insulating film having a step difference, a gate electrode having a step difference, a drain region including first, second, and third impurity regions, a source region including first and third impurity regions, a spacer, an interlayer dielectric film and a metal electrode. Threshold voltage can be maintained to an appropriate level, junction break voltage can be increased, and the punchthrough characteristic can also be enhanced.
Inventors
- 👤 Yong-bae Choi
- 👤 Keon-Soo Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:25
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
225 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said channel region comprises a first channel region at low concentration and a second channel region at high concentration formed by ion-implanted impurities of the same conductivity type as that of the semiconductor substrate; and wherein a first gate insulating film region is formed on said first channel region, and a second gate insulating film region is formed on said second channel region.
Claim 2
Dependent Claim
225 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said channel region comprises a first channel region at low concentration and a second channel region at high concentration formed by ion-implanted impurities of the same conductivity type as that of the semiconductor substrate; and wherein a first gate insulating film region is formed on said first channel region, and a second gate insulating film region is formed on said second channel region.
Claim 3
Dependent Claim
33 words
A high withstand voltage transistor according to claim 1, wherein said first gate insulating film region comprises a thick insulating film and said second gate insulating film region comprises a thin insulating film.
Claim 4
Dependent Claim
31 words
A high withstand voltage transistor according to claim 1, wherein said first channel region is adjacent to said drain region, and said second region is formed adjacent to said source region.
Claim 5
Dependent Claim
211 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said gate insulating film comprises a thick first gate insulating film region and a thin second gate insulating film region; and wherein said first gate insulating film region is formed on a first channel region, and said second gate insulating film region is formed on a second channel region.
Claim 6
Dependent Claim
211 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said gate insulating film comprises a thick first gate insulating film region and a thin second gate insulating film region; and wherein said first gate insulating film region is formed on a first channel region, and said second gate insulating film region is formed on a second channel region.
Claim 7
Dependent Claim
44 words
A high withstand voltage transistor according to claim 4, wherein said first channel region comprises a low concentration of impurities and said second channel region includes a high concentration of impurities, said impurities being the same conductivity type as that of said semiconductor substrate.
Claim 8
Dependent Claim
31 words
A high withstand voltage transistor according to claim 4, wherein said first channel region is adjacent to said drain region, and said second region is formed adjacent to said source region.
Claim 9
Dependent Claim
197 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said drain region includes shallow first and deep second impurity regions at low concentration formed of an opposite conductive impurity to that of said semiconductor substrate and a shallow third impurity region at high concentration.
Claim 10
Dependent Claim
197 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said drain region includes shallow first and deep second impurity regions at low concentration formed of an opposite conductive impurity to that of said semiconductor substrate and a shallow third impurity region at high concentration.
Claim 11
Dependent Claim
21 words
A high withstand voltage transistor according to claim 7, wherein said second impurity region is arranged below said third impurity region.
Claim 12
Dependent Claim
38 words
A high withstand voltage transistor according to claim 7, wherein said third impurity region is formed spaced from said gate electrode by a predetermined distance so that said third impurity region does not overlap with said gate electrode.
Claim 13
Dependent Claim
183 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said source region includes a shallow first impurity region at low concentration and a shallow third impurity region at high concentration.
Claim 14
Dependent Claim
183 words
A high withstand voltage transistor comprising: a semiconductor substrate; a channel stop region located on said substrate and formed of the same impurity as that of said substrate; field oxide films formed on said channel stop region; a channel region having a nonuniform impurity concentration on an active region between said field oxide films; a gate insulating film having a step difference formed on said channel region; a source and drain region having asymmetrical impurity distribution on both sides of said channel region, said source and drain region being LDD structures and said asymmetrical impurity distribution of said source and drain region having n + and n - type impurities, respectively; a gate electrode having a step difference formed on said gate insulating film; a spacer formed on the sidewalls of said gate electrode; an interlayer dielectric film having a contact hole formed on the whole surface of the resultant structure; and a metal electrode formed by filling said contact hole; wherein said source region includes a shallow first impurity region at low concentration and a shallow third impurity region at high concentration.
Claim 15
Dependent Claim
38 words
A high withstand voltage transistor according to claim 10, wherein said third impurity region is formed spaced from said gate electrode by a predetermined distance so that said third impurity region does not overlap with said gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |