Short channel mosfet with buried anti-punch through region

Claim 2

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein: said transistor comprises: an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and a low resistivity and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) said semiconductor substrate has a high impurity concentration and has a conductivity type opposite to that of said source region; (b) said semiconductor device further includes, at a surface of said substrate, a region of a lesser impurity concentration than that of said substrate and of a conductivity type being the same as that of said substrate thereby to define an implanted region of higher doping concentration that is positioned lower than and effectively separated from the source region and that does not appreciably increase junction capacitance between said defined implanted region and the source region; (c) said source region, said drain region and said channel region are formed in said region of a lesser impurity concentration; (d) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region (12) and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (e) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (f) said gate insulator layer is less than 500Å, and (g) the relationship L/D>0.9, where L represents the channel length and D represents the depth from the surface to said semiconductor substrate.

Claim 3

A semiconductor device according to claim 1 characterized in that the gate electrode is formed on the drain region via a thin insulator layer so that a storage capacitor is formed by this insulator layer, the drain region and the electrode.

Claim 4

A semiconductor device having a complementary inverter circuit comprising an n-channel insulated-gate transistor and a p-channel insulated-gate transistor connected in series to said n-channel insulated-gate transistor, gates of these transistors being directly connected to each other, wherein: each of these transistors has a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and a low resistivity and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) said semiconductor substrate has a high impurity concentration and has a conductivity type opposite to that of said source regions; (b) said semiconductor device further includes, at a surface of said substrate, a region of a lesser impurity concentration than that of said substrate and of a conductivity type being the same as that of said substrate thereby to define an implanted region of higher doping concentration that is positioned lower than and effectively separated from the source region and that does not appreciably increase junction capacitance between said defined implanted region and the source region; (c) said source region, said drain region and said channel region are formed in said region of a lesser concentration; (d) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region (12) and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (e) an effective channel-length of less than 1 μm is defined by the distance between said source and said drain regions; (f) said gate insulator layer is less than 500Å, and (g) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor substrate.

Claim 5

A semiconductor device having a complementary inverter circuit comprising an n-channel insulated-gate transistor and a p-channel insulated-gate transistor connected in series to said n-channel insulated-gate transistor, gates of these transistors being directly connected to each other, wherein: each of these transistors has a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and a low resistivity and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) said semiconductor substrate has a high impurity concentration and has a conductivity type opposite to that of said source regions; (b) said semiconductor device further includes, at a surface of said substrate, a region of a lesser impurity concentration than that of said substrate and of a conductivity type being the same as that of said substrate thereby to define an implanted region of higher doping concentration that is positioned lower than and effectively separated from the source region and that does not appreciably increase junction capacitance between said defined implanted region and the source region; (c) said source region, said drain region and said channel region are formed in said region of a lesser concentration; (d) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region (12) and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (e) an effective channel-length of less than 1 μm is defined by the distance between said source and said drain regions; (f) said gate insulator layer is less than 500Å, and (g) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor substrate.

Claim 6

An MOS device comprising: A. a substrate having a surface, B. a low-resistive source region having a first conductivity type located on the surface of said substrate, C. a low-resistive drain region having said first conductivity type located in said substrate, D. a high-resistive channel region having a second conductivity type located between said source and drain regions, said channel region having an effective length of less than 1 μm across which current flows between said source and drain regions, E. a highly-doped polysilicon gate electrode of said second conductivity type including a gate insulator of less than 500Å located on the surface of the substrate for controlling current between said source and drain regions, said polysilicon gate electrode having a relatively high built-in voltage relative to said source region, F. a deeply implanted semiconductive region of said second conductivity type having an impurity concentration higher than said channel region and extending along at least a portion of said effective channel length L, said implanted region being effectively separated from the source region and located at a depth D sufficiently beneath the surface of said substrate so as to reduce the junction capacitance between the implanted region and the source region, and G. said channel region being configured such that the ratio L/D is greater than 0.9.

Claim 7

An MOS device comprising: A. a substrate having a surface, B. a low-resistive source region having a first conductivity type located on the surface of said substrate, C. a low-resistive drain region having said first conductivity type located in said substrate, D. a high-resistive channel region having a second conductivity type located between said source and drain regions, said channel region having an effective length of less than 1 μm across which current flows between said source and drain regions, E. a highly-doped polysilicon gate electrode of said second conductivity type including a gate insulator of less than 500Å located on the surface of the substrate for controlling current between said source and drain regions, said polysilicon gate electrode having a relatively high built-in voltage relative to said source region, F. a deeply implanted semiconductive region of said second conductivity type having an impurity concentration higher than said channel region and extending along at least a portion of said effective channel length L, said implanted region being effectively separated from the source region and located at a depth D sufficiently beneath the surface of said substrate so as to reduce the junction capacitance between the implanted region and the source region, and G. said channel region being configured such that the ratio L/D is greater than 0.9.

Claim 8

An MOS device as recited in claim 4 wherein said deeply implanted region comprises a buried p+ region.

Claim 9

An MOS device as recited in claim 5 wherein the buried p+ region lies at a depth lower than said source and drain regions and being effectively separated from said source region so as to reduce junction capacitance at the junction between the source and buried p+ regions.

Claim 10

A one-transistor memory device including an MOS device as recited in claim 6 for controlling access to data contained in said memory device.