US4247862A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ionization resistant MOS structure
Assignee: Intel Corp
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Filing: 1978-07-05
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Granted: 1981-01-27
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Expires: 1998-07-05
Abstract
Abstract A structure and method for preventing minority carriers caused by an alpha particle, or the like, from drifting into storage regions and causing a false data bit. In a high density MOS circuit, a single alpha particle including one originating within the substrate or circuit package can generate enough carriers to give a false data bit. A minority carrier reflective barrier is employed to prevent substantial numbers of minority carriers from drifting into the active layer. In the presently preferred embodiment, this barrier is formed by ion implanting the upper surface of the substrate.
Inventors
- 👤 Raphael Klein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:59
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10B; H10B12/00; H10P30/202; H10P30/204; H10W; H10W42/00; H10W42/20; H10W42/25; Y; Y10; Y10S; Y10S257/00; Y10S257/921; Y10S438/00; Y10S438/953
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
In an MOS integrated circuit where a plurality of field-effect devices are formed on the upper surface of a semiconductor body, a structure for preventing failures from ionization within said body comprising: nonuniform doping within the upper regions of said body below said upper surface, said nonuniform doping providing a gradient with a lower dopant concentration towards the interior of said body and a higher dopant concentration towards said upper surface, such that an electric field is established which repels minority carriers generated in said body so as to prevent them from entering said upper surface, whereby minority carriers will not drift into the active circuit devices.
Claim 2
Dependent Claim
107 words
In an MOS integrated circuit where a plurality of field-effect devices are formed on the upper surface of a semiconductor body, a structure for preventing failures from ionization within said body comprising: nonuniform doping within the upper regions of said body below said upper surface, said nonuniform doping providing a gradient with a lower dopant concentration towards the interior of said body and a higher dopant concentration towards said upper surface, such that an electric field is established which repels minority carriers generated in said body so as to prevent them from entering said upper surface, whereby minority carriers will not drift into the active circuit devices.
Claim 3
Dependent Claim
17 words
The structure defined by claim 1 wherein said nonuniform doping is formed by ion implanting said body.
Claim 4
Dependent Claim
22 words
The structure defined by claim 2 wherein said body is a p-type body and wherein boron is used for said ion implanting.
Claim 5
Dependent Claim
22 words
The structure defined by claim 1 wherein said nonuniform doping is formed by a heavily doped epitaxial layer formed on a substrate.
Claim 6
Dependent Claim
23 words
The structure defined by claim 4 including a second epitaxial layer formed on said heavily doped layer for receiving said active circuit devices.
Claim 7
Dependent Claim
125 words
In the fabrication of an MOS integrated circuit on the surface of a silicon substrate, a process for preparing said substrate for receiving said integrated circuit, such that said circuit is substantially immune to failures which result from ionization within said substrate thereby allowing minority carriers to drift into said circuit causing said failures, comprising the step of: ion implanting said surface of said substrate so as to form a dopant gradient in the upper regions of said substrate which varies from a lower dopant concentration towards the interior said substrate to a higher dopant concentration in the direction of said surface, whereby said dopant gradient provides an electrical field which repels said minority carriers so as to prevent them from interfering with said circuit.
Claim 8
Dependent Claim
125 words
In the fabrication of an MOS integrated circuit on the surface of a silicon substrate, a process for preparing said substrate for receiving said integrated circuit, such that said circuit is substantially immune to failures which result from ionization within said substrate thereby allowing minority carriers to drift into said circuit causing said failures, comprising the step of: ion implanting said surface of said substrate so as to form a dopant gradient in the upper regions of said substrate which varies from a lower dopant concentration towards the interior said substrate to a higher dopant concentration in the direction of said surface, whereby said dopant gradient provides an electrical field which repels said minority carriers so as to prevent them from interfering with said circuit.
Claim 9
Dependent Claim
19 words
The process defined by claim 6 wherein said substrate is ion implanted to a depth of approximately two microns.
Claim 10
Dependent Claim
14 words
The process defined by claim 7 wherein said ion implantation employs a boron impurity.
Claim 11
Dependent Claim
27 words
The process defined by claim 6 wherein said substrate is a p-type substrate with an impurity level of between 10 13 and 10 15 atoms/cm 3 .
Claim 12
Dependent Claim
24 words
The process defined by claim 6 wherein said ion implantation provides an impurity level of between 10 15 and 10 17 atoms/cm 3 .
References Cited (Backward Citations)
US4113513A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-27 | 1984-07-28 | 1985-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-27 | 1988-07-28 | 1989-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-27 | 1992-07-28 | 1993-01-27 | $7700.00 | Window Closed / Lapsed |