Short channel MOSFET with buried anti-punch through region

Claim 2

A semiconductor device formed with an insulation-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistance and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and a drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, wherein: at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is selected from a group consisting of a metal, a metal silicide and a highly-doped polysilicon of a conductivity type opposite to that of said source region, a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region; an effective channel length of less than 1 μm defined by the distance between said source and said drain regions, said gate insulator layer being less than 500 Å, and the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface of said semiconductor region.

Claim 3

A semiconductor device according to claim 1, in which said metal is one selected from a group consisting of platinum, molybdem and tungsten.

Claim 4

A semiconductor device according to claim 1, in which said metal silicide is selected from a group consisting of molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide and platinum silicide.

Claim 5

A semiconductor device according to claim 1, in which said buried region extends to contact said drain region.

Claim 6

A semiconductor device according to claim 1, in which said buried region extends close to said drain region.

Claim 7

A semiconductor device according to claim 1, in which said buried region extends to both of said drain region and said source region.

Claim 8

A semiconductor device according to claim 1, in which said semiconductor substrate has a high impurity concentration and has a conductivity type opposite to that of said source region, said semiconductor device further includes, at a surface of said substrate, a region of a lesser impurity concentration that of said substrate and of a conductivity type same as that of said substrate, and said source region, said drain region and said channel region are formed in said region of a lesser impurity concentration.

Claim 9

A semiconductor device according to claim 1, in which said buried region has such an impurity concentration gradient that the degree of concentration is lower progressively toward the interior of said substrate from said surface thereof.

Claim 10

A semiconductor device according to claim 1 in which said insulation-gate transistor constitutes a memory cell of a dynamic random access memory.

Claim 11

A semiconductor device according to claim 9, in which the electrode is formed on the drain region via a thin insulator layer so that a storage capacitor is formed by this insulator layer, the drain region and the electrode.

Claim 12

A semiconductor device according to claim 9, in which a storage capacitor is formed in said drain region.

Claim 13

A semiconductor device according to claim 10, in which said source region serves as a bit line, and said gate electrode serves as a word line.

Claim 14

A semiconductor device according to claim 1, in which said insulation-gate transistor serves as one of transistors constituting a complementary inverter circuit.

Claim 15

A semiconductor device according to claim 11 in which said source region serves as a bit line and said gate electrode serves as a word line.

Claim 16

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein: said transistor comprises; an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and resistivity and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region (12) and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region said source region; (c) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (d) said gate insulator layer is less than 500 Å, (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region.

Claim 17

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein: said transistor comprises; an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and resistivity and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region (12) and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region said source region; (c) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (d) said gate insulator layer is less than 500 Å, (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region.

Claim 18

A semiconductor device according to claim 15 characterized in that the electrode is formed on the drain region via a thin insulator layer so that a storage capacitor is formed by this insulator layer, the drain region and the electrode.

Claim 19

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein: said transistor comprises: an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region formed with an inversion region and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length including beneath said drain region, but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region; (c) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (d) said gate insulator layer is less than 500 Å, and (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region, said one storage capacitor comprising an inversion region serving as a drain region and an insulator layer and an electrode formed above said inversion region.

Claim 20

A dynamic random access memory comprising at least one insulated gate transistor and one storage capacitor, wherein: said transistor comprises: an insulated-gate transistor having a semiconductor substrate, and having, closer to a surface of said substrate, a source semiconductor region of one conductivity type and a low resistivity, a drain region formed with an inversion region and a channel semiconductor region of the opposite conductivity type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is a metal, a metal silicide, or a highly-doped polysilicon of a conductivity type opposite to that of said source region; (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length including beneath said drain region, but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region; (c) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (d) said gate insulator layer is less than 500 Å, and (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region, said one storage capacitor comprising an inversion region serving as a drain region and an insulator layer and an electrode formed above said inversion region.

Claim 21

A semiconductor device according to claim 17, in which said source region serves as a bit line, and said gate electrode serve as a word line.

Claim 22

A semiconductor device having a complementary inverter circuit comprising an n-channel insulated-gate transistor and a p-channel insulated-gate transistor connected in series to said n-channel insulated-gate transistor, gates of these transistors being directly connected to each other, wherein: each of these transistors has a semiconductor substrate, and having, closer to a surface of said substrate, a source of semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and a low resistivity and a channel semiconductor region of the opposite type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is a metal, a metal silicide, or a highly-doped polysilicon of conductivity type opposite to that of said source region; (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region; (c) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (d) said gate insulator layer is less than 500 Å, and (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region, said one storage capacitor comprising an inversion region serving as a drain region and an insulator layer and an electrode formed above said inversion region.

Claim 23

A semiconductor device having a complementary inverter circuit comprising an n-channel insulated-gate transistor and a p-channel insulated-gate transistor connected in series to said n-channel insulated-gate transistor, gates of these transistors being directly connected to each other, wherein: each of these transistors has a semiconductor substrate, and having, closer to a surface of said substrate, a source of semiconductor region of one conductivity type and a low resistivity, a drain region having said one conductivity type and a low resistivity and a channel semiconductor region of the opposite type and a high resistivity defined between said source region and drain region, and having a gate electrode formed on a surface of said channel region via a gate insulator layer, characterized in that (a) at least a portion of said gate electrode contacting said gate insulator layer is formed with a material which has a relatively high built-in voltage relative to said source region and which is a metal, a metal silicide, or a highly-doped polysilicon of conductivity type opposite to that of said source region; (b) a deep semiconductor region (33) of said opposite conductivity type having an impurity concentration higher than that of the channel region and extending along at least a part of said effective channel length but being effectively separated from and located at a depth sufficiently lower than said source region so as to reduce junction capacitance between said deep region and said source region; (c) an effective channel length of less than 1 μm is defined by the distance between said source and said drain regions; (d) said gate insulator layer is less than 500 Å, and (e) the relationship L/D>0.9, where L represents the effective channel length and D represents the depth from the surface to said semiconductor region, said one storage capacitor comprising an inversion region serving as a drain region and an insulator layer and an electrode formed above said inversion region.