US5786618A
Expired / Lapsed
US
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ROM memory cell with non-uniform threshold voltage
Assignee: United Microelectronics Corp
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Filing: 1996-03-21
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Granted: 1998-07-28
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Expires: 2016-03-21
Abstract
Abstract The present invention features a ROM memory cell with a non-uniform threshold voltage. The ROM memory cell includes a channel region divided into several channels deposed in parallel along the axial direction of carrier transport. Afterwards, one code-implant procedure is performed to program the memory cell to store one of multiple states, thereby constituting a multiple-state ROM, the fabrication of which does not require multiple photolithography as well as multiple implantation processes.
Inventors
- 👤 Jemmy Wen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:22
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/387
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
232 words
A memory comprising: a semiconductor substrate having isolation structures formed thereon to define a plurality of active regions, wherein the plurality of active regions are divided into subsets, there being a first subset, a second subset, a third subset, and a fourth subset; above each of said active regions, a gate stack on said substrate within that active region; in each of said active regions, source and drain regions in said substrate separated on opposite sides of said gate stack; in each of said active regions, a channel region in said substrate below said gate stack and between said source and drain regions, said channel region comprising a first channel and a second channel deposed in parallel with each other and provided with different threshold voltages; in each of said active regions of the first subset, impurities implanted in both the first and second channels to produce a first programmed state; in each of said active regions of the second subset, impurities implanted in the first channel but not the second channel to produce a second programmed state; in each of said active regions of the third subset, impurities implanted in the second channel but not the first channel to produce a third programmed state; in each of said active regions of the fourth subset, impurities implanted in neither the first channel nor the second channel to produce a fourth programmed state.
Claim 2
Dependent Claim
232 words
A memory comprising: a semiconductor substrate having isolation structures formed thereon to define a plurality of active regions, wherein the plurality of active regions are divided into subsets, there being a first subset, a second subset, a third subset, and a fourth subset; above each of said active regions, a gate stack on said substrate within that active region; in each of said active regions, source and drain regions in said substrate separated on opposite sides of said gate stack; in each of said active regions, a channel region in said substrate below said gate stack and between said source and drain regions, said channel region comprising a first channel and a second channel deposed in parallel with each other and provided with different threshold voltages; in each of said active regions of the first subset, impurities implanted in both the first and second channels to produce a first programmed state; in each of said active regions of the second subset, impurities implanted in the first channel but not the second channel to produce a second programmed state; in each of said active regions of the third subset, impurities implanted in the second channel but not the first channel to produce a third programmed state; in each of said active regions of the fourth subset, impurities implanted in neither the first channel nor the second channel to produce a fourth programmed state.
Claim 3
Dependent Claim
24 words
The memory of claim 1, wherein said semiconductor substrate and said impurities in the channel regions of said plurality of active regions are P-type.
Claim 4
Dependent Claim
24 words
The memory of claim 1, wherein said semiconductor substrate and said impurities in the channel regions of said plurality of active regions are N-type.
Claim 5
Dependent Claim
26 words
The memory of claim 1, wherein said semiconductor substrate is P-type and said impurities in the channel regions of said plurality of active regions are N-type.
Claim 6
Dependent Claim
26 words
The memory of claim 1, wherein said semiconductor substrate is N-type and said impurities in the channel regions of said plurality of active regions are P-type.
Claim 7
Dependent Claim
30 words
The memory of claim 1, wherein the gate stack over each of said active regions comprises a gate dielectric layer and a gate electrode formed over said gate dielectric layer.
References Cited (Backward Citations)
US4395725A
Cited
US4549336A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-07-27 | 2002-01-26 | 2002-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-27 | 2006-01-26 | 2006-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-27 | 2010-01-26 | 2010-07-28 | $7700.00 | Window Closed / Lapsed |