US5698884A
Expired / Lapsed
US
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Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricating same
Assignee: Thunderbird Technologies Inc
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Filing: 1996-02-07
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Granted: 1997-12-16
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Expires: 2016-02-07
Abstract
Abstract A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region. Higher carrier mobility in the channel may thereby be obtained for a given doping level.
Inventors
- 👤 Michael W. Dennen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/637; H10D30/01; H10D30/021; H10D30/0223; H10D30/027; H10D30/0278; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
183 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; a first tub region of second conductivity type in said substrate at a surface thereof, extending into said substrate to a first depth from said substrate surface; a second tub region of said first conductivity type in said first tub region, extending into said substrate to a second depth from said substrate surface, wherein said second depth is less than said first depth; a third tub region of said second conductivity type in said second tub region, extending into said substrate to a third depth from said substrate surface, wherein said third depth is less than said second depth; spaced apart source and drain regions of said second conductivity type in said first tub region, extending into said substrate to a fourth depth from said substrate surface, wherein said fourth depth is greater than said third depth; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively.
Claim 2
Dependent Claim
183 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; a first tub region of second conductivity type in said substrate at a surface thereof, extending into said substrate to a first depth from said substrate surface; a second tub region of said first conductivity type in said first tub region, extending into said substrate to a second depth from said substrate surface, wherein said second depth is less than said first depth; a third tub region of said second conductivity type in said second tub region, extending into said substrate to a third depth from said substrate surface, wherein said third depth is less than said second depth; spaced apart source and drain regions of said second conductivity type in said first tub region, extending into said substrate to a fourth depth from said substrate surface, wherein said fourth depth is greater than said third depth; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively.
Claim 3
Dependent Claim
19 words
A field effect transistor according to claim 1 wherein said fourth depth is also greater than said second depth.
Claim 4
Dependent Claim
19 words
A field effect transistor according to claim 2 wherein said fourth depth is also less than said first depth.
Claim 5
Dependent Claim
19 words
A field effect transistor according to claim 1 wherein said fourth depth is also less than said first depth.
Claim 6
Dependent Claim
22 words
A field effect transistor according to claim 1 wherein said gate electrode includes a polycrystalline silicon layer of said first conductivity type.
Claim 7
Dependent Claim
174 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; spaced apart source and drain regions of second conductivity type in said substrate at a surface thereof; a first layer of said second conductivity type in said substrate at said substrate surface, extending from said source region to said drain region and extending into said substrate to a first depth from said substrate surface; a second layer of said first conductivity type in said substrate, extending from said source region to said drain region and extending into said substrate from said first depth to a second depth from said substrate surface; a third layer of said second conductivity type in said substrate, extending from said source region to said drain region and extending into said substrate from said second depth to a third depth from said substrate surface; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively.
Claim 8
Dependent Claim
174 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; spaced apart source and drain regions of second conductivity type in said substrate at a surface thereof; a first layer of said second conductivity type in said substrate at said substrate surface, extending from said source region to said drain region and extending into said substrate to a first depth from said substrate surface; a second layer of said first conductivity type in said substrate, extending from said source region to said drain region and extending into said substrate from said first depth to a second depth from said substrate surface; a third layer of said second conductivity type in said substrate, extending from said source region to said drain region and extending into said substrate from said second depth to a third depth from said substrate surface; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; and source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively.
Claim 9
Dependent Claim
39 words
A field effect transistor according to claim 6 wherein said source and drain regions include source and drain bottoms in said semiconductor substrate, and wherein said second and third layers extend from said source bottom to said drain bottom.
Claim 10
Dependent Claim
37 words
A field effect transistor according to claim 6 wherein said source and drain regions include source and drain bottoms in said semiconductor substrate, and wherein said third layer extends from said source bottom to said drain bottom.
Claim 11
Dependent Claim
22 words
A field effect transistor according to claim 6 wherein said gate electrode includes a polycrystalline silicon layer of said first conductivity type.
Claim 12
Dependent Claim
134 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a buried region of said first conductivity type in said tub region and extending beneath said substrate surface from said source region to said drain region; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively; wherein said source and drain regions include source and drain bottoms in said semiconductor substrate, and wherein said buried region further extends from said source bottom to said drain bottom.
Claim 13
Dependent Claim
134 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; a tub region of second conductivity type in said substrate at a surface thereof; spaced apart source and drain regions of said second conductivity type in said tub region at said substrate surface; a buried region of said first conductivity type in said tub region and extending beneath said substrate surface from said source region to said drain region; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively; wherein said source and drain regions include source and drain bottoms in said semiconductor substrate, and wherein said buried region further extends from said source bottom to said drain bottom.
Claim 14
Dependent Claim
22 words
A field effect transistor according to claim 10 wherein said gate electrode includes a polycrystalline silicon layer of said first conductivity type.
Claim 15
Dependent Claim
141 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; spaced apart source and drain regions of second conductivity type in said substrate at a surface thereof; a first layer of said second conductivity type in said substrate at said substrate surface, extending from said source region to said drain region; a buried second layer of said first conductivity type in said first layer, extending beneath said substrate surface from said source region to said drain region; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively; wherein said source and drain regions include source and drain bottoms in said substrate, and wherein said first layer further extends from said source bottom to said drain bottom.
Claim 16
Dependent Claim
141 words
A field effect transistor comprising: a semiconductor substrate of first conductivity type; spaced apart source and drain regions of second conductivity type in said substrate at a surface thereof; a first layer of said second conductivity type in said substrate at said substrate surface, extending from said source region to said drain region; a buried second layer of said first conductivity type in said first layer, extending beneath said substrate surface from said source region to said drain region; a gate insulating layer on said substrate surface, between said spaced apart source and drain regions; source, drain and gate electrodes contacting said source and drain regions and said gate insulating layer, respectively; wherein said source and drain regions include source and drain bottoms in said substrate, and wherein said first layer further extends from said source bottom to said drain bottom.
Claim 17
Dependent Claim
42 words
A field effect transistor according to claim 12 wherein said source and drain regions include source and drain bottoms in said substrate, and wherein said first layer and said buried second layer both extend from said source bottom to said drain bottom.
Claim 18
Dependent Claim
22 words
A field effect transistor according to claim 12 wherein said gate electrode includes a polycrystalline silicon layer of said first conductivity type.
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