Fermi threshold field effect transistor with reduced gate and diffusion capacitance

Claim 2

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface and extending a first predetermined depth from said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface and extending a second predetermined depth from said first surface, wherein said first predetermined depth is greater than said second predetermined depth, said tub region being free of a region of said first conductivity type between said spaced apart source and drain regions of said second conductivity type; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions and extending a third predetermined depth from said first surface, said third predetermined depth being less than said second predetermined depth; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 3

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface, wherein said tub region extends a second predetermined depth from said channel, wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 4

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface, wherein said tub region extends a second predetermined depth from said channel, wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 5

The field effect transistor of claim 2 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 6

The field effect transistor of claim 3 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 7

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to produce zero static electric field perpendicular to said first surface at said first predetermined depth.

Claim 8

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to produce zero static electric field perpendicular to said first surface at said first predetermined depth.

Claim 9

The field effect transistor of claim 5 wherein at least one of said first and second predetermined depths are further selected to produce zero static electric field perpendicular to said first surface from said first predetermined depth to said first surface, upon application of the threshold voltage of said field effect transistor to said gate contact.

Claim 10

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said tub region extends a predetermined depth from said first surface, at least said predetermined depth being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate.

Claim 11

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said tub region extends a predetermined depth from said first surface, at least said predetermined depth being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate.

Claim 12

The field effect transistor of claim 1 wherein at least said first predetermined depth is selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate.

Claim 13

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said channel region, extending from said first predetermined depth towards said first surface upon application of voltage to said gate contact beyond the threshold voltage of said field effect transistor.

Claim 14

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said channel region, extending from said first predetermined depth towards said first surface upon application of voltage to said gate contact beyond the threshold voltage of said field effect transistor.

Claim 15

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively; wherein said tub region extends a predetermined depth from said first surface, at least said predetermined depth being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said tub region, extending from a second predetermined depth between said predetermined depth and said first surface towards said first surface, upon application of voltage to said gate contact beyond the threshold voltage of said field effect transistor.

Claim 16

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively; wherein said tub region extends a predetermined depth from said first surface, at least said predetermined depth being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said tub region, extending from a second predetermined depth between said predetermined depth and said first surface towards said first surface, upon application of voltage to said gate contact beyond the threshold voltage of said field effect transistor.

Claim 17

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to allow carriers of said second conductivity type to flow within said channel region, from said source region to said drain region and beneath said first surface, without creating an inversion layer in said channel.

Claim 18

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to allow carriers of said second conductivity type to flow within said channel region, from said source region to said drain region and beneath said first surface, without creating an inversion layer in said channel.

Claim 19

The field effect transistor of claim 1 wherein at least said first predetermined depth is selected to allow carriers of said second conductivity type to flow within said tub region, from said source region to said drain region and beneath said first surface, without creating an inversion layer in said tub region.

Claim 20

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to produce a first gate capacitance upon biasing said gate contact from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate contact from above said threshold voltage to said threshold voltage.

Claim 21

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to produce a first gate capacitance upon biasing said gate contact from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate contact from above said threshold voltage to said threshold voltage.

Claim 22

The field effect transistor of claim 1 wherein at least said first predetermined depth is selected to produce a first gate capacitance upon biasing said gate contact from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate contact from above said threshold voltage to said threshold voltage.

Claim 23

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, wherein said gate contact includes a polysilicon layer of said first conductivity type and a gate electrode on said polysilicon layer opposite said gate insulating layer; at least one of said first and second predetermined depths being selected to produce a voltage at said first surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode.

Claim 24

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, wherein said gate contact includes a polysilicon layer of said first conductivity type and a gate electrode on said polysilicon layer opposite said gate insulating layer; at least one of said first and second predetermined depths being selected to produce a voltage at said first surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode.

Claim 25

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said tub region extends a predetermined depth from said first surface, wherein said gate contact includes a polysilicon layer of said first conductivity type and a gate electrode on said polysilicon layer opposite said gate insulating layer; at least said predetermined depth being selected to produce a voltage at said first surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode.

Claim 26

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said tub region extends a predetermined depth from said first surface, wherein said gate contact includes a polysilicon layer of said first conductivity type and a gate electrode on said polysilicon layer opposite said gate insulating layer; at least said predetermined depth being selected to produce a voltage at said first surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode.

Claim 27

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to change the threshold voltage of said field effect transistor by less than one twentieth of a volt, when the voltage applied to said substrate contact changes by one volt.

Claim 28

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said channel extends a first predetermined depth from said first surface and said tub region extends a second predetermined depth from said channel, at least one of said first and second predetermined depths being selected to change the threshold voltage of said field effect transistor by less than one twentieth of a volt, when the voltage applied to said substrate contact changes by one volt.

Claim 29

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said tub region extends a predetermined depth from said first surface, at least said predetermined depth being selected to change the threshold voltage of said field effect transistor by less than one twentieth of a volt, when the voltage applied to said substrate contact changes by one volt.

Claim 30

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; and a substrate contact for electrically contacting said substrate; wherein said tub region extends a predetermined depth from said first surface, at least said predetermined depth being selected to change the threshold voltage of said field effect transistor by less than one twentieth of a volt, when the voltage applied to said substrate contact changes by one volt.

Claim 31

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said substrate is doped at a doping density N s , has an intrinsic carrier concentration N i at temperature T degrees Kelvin and a permittivity e s ; said field effect transistor further comprising a substrate contact for electrically contacting said substrate; wherein said channel extends a first predetermined depth Y f from said first surface and said tub region extends a second predetermined depth Y o from said channel; wherein said tub region is doped at a doping density which is a factor α times N s ; wherein said gate contact includes a polysilicon layer of said first conductivity type and which is doped at a doping density N p ; wherein said first predetermined depth Y f is equal to ##EQU45## where q is 1.6×10 -19 coulombs and K is 1.38×10 -23 Joules/°Kelvin.

Claim 32

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface; a tub region of second conductivity type in said substrate at said first surface; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions; a gate insulating layer on said substrate at said first surface, between said spaced apart source and drain regions; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively; wherein said substrate is doped at a doping density N s , has an intrinsic carrier concentration N i at temperature T degrees Kelvin and a permittivity e s ; said field effect transistor further comprising a substrate contact for electrically contacting said substrate; wherein said channel extends a first predetermined depth Y f from said first surface and said tub region extends a second predetermined depth Y o from said channel; wherein said tub region is doped at a doping density which is a factor α times N s ; wherein said gate contact includes a polysilicon layer of said first conductivity type and which is doped at a doping density N p ; wherein said first predetermined depth Y f is equal to ##EQU45## where q is 1.6×10 -19 coulombs and K is 1.38×10 -23 Joules/°Kelvin.

Claim 33

The field effect transistor of claim 19 wherein said second predetermined depth Y o is equal to ##EQU46## where φ s is equal to 2φ f +KT/q Lnα, and φ f is the Fermi potential of said semiconductor substrate.

Claim 34

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel, at least one of said first and second predetermined depths and said first and second doping densities being selected to produce zero static electric field perpendicular to said first surface at said first predetermined depth; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 35

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel, at least one of said first and second predetermined depths and said first and second doping densities being selected to produce zero static electric field perpendicular to said first surface at said first predetermined depth; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 36

The field effect transistor of claim 21 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 37

The field effect transistor of claim 22 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 38

The field effect transistor of claim 23 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 39

The field effect transistor of claim 21 wherein at least one of said first and second predetermined depths and first and second doping densities are further selected to produce zero static electric field perpendicular to said first surface from said first predetermined depth to said first surface upon application of the threshold voltage of said field effect transistor to said gate contact.

Claim 40

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel, at least one of said first and second predetermined depths and said first and second doping densities being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 41

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel, at least one of said first and second predetermined depths and said first and second doping densities being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said semiconductor substrate; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 42

The field effect transistor of claim 26 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 43

The field effect transistor of claim 27 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 44

The field effect transistor of claim 28 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 45

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively, at least one of said first and second predetermined depths and said first and second doping densities being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said channel region, extending from said first predetermined depth towards said first surface upon application of voltage to said gate contact beyond the threshold voltage of said field effect transistor.

Claim 46

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively, at least one of said first and second predetermined depths and said first and second doping densities being selected to allow carriers of said second conductivity type to flow from said source region to said drain region in said channel region, extending from said first predetermined depth towards said first surface upon application of voltage to said gate contact beyond the threshold voltage of said field effect transistor.

Claim 47

The field effect transistor of claim 30 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 48

The field effect transistor of claim 31 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 49

The field effect transistor of claim 32 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 50

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel, at least one of said first and second predetermined depths and said first and second doping densities being selected to allow carriers of said second conductivity type to flow within said channel region, from said source region to said drain region and beneath said first surface, without creating an inversion layer in said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 51

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel, at least one of said first and second predetermined depths and said first and second doping densities being selected to allow carriers of said second conductivity type to flow within said channel region, from said source region to said drain region and beneath said first surface, without creating an inversion layer in said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively.

Claim 52

The field effect transistor of claim 34 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 53

The field effect transistor of claim 35 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 54

The field effect transistor of claim 36 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 55

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively, at least one of said first and second predetermined depths and said first and second doping densities being selected to produce a first gate capacitance upon biasing said gate contact from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate contact from above said threshold voltage to said threshold voltage.

Claim 56

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain and gate contacts for contacting said source and drain regions and said gate insulating layer, respectively, at least one of said first and second predetermined depths and said first and second doping densities being selected to produce a first gate capacitance upon biasing said gate contact from below the threshold voltage of said field effect transistor to said threshold voltage, and to produce a second gate capacitance upon biasing said gate contact from above said threshold voltage to said threshold voltage.

Claim 57

The field effect transistor of claim 38 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 58

The field effect transistor of claim 39 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 59

The field effect transistor of claim 40 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 60

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain, substrate and gate contacts for contacting said source and drain regions, said substrate and said gate insulating layer, respectively, said gate contact including a polysilicon layer of said first conductivity type and a gate electrode on said polysilicon layer opposite said gate insulating layer; at least one of said first and second predetermined depths and said first and second doping densities being selected to produce a voltage at said first surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode.

Claim 61

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain, substrate and gate contacts for contacting said source and drain regions, said substrate and said gate insulating layer, respectively, said gate contact including a polysilicon layer of said first conductivity type and a gate electrode on said polysilicon layer opposite said gate insulating layer; at least one of said first and second predetermined depths and said first and second doping densities being selected to produce a voltage at said first surface, adjacent said gate insulating layer, which is equal and opposite to the sum of the voltage between said substrate contact and said substrate and between said polysilicon layer and said gate electrode.

Claim 62

The field effect transistor of claim 42 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 63

The field effect transistor of claim 43 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 64

The field effect transistor of claim 44 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 65

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain, substrate and gate contacts for contacting said source and drain regions, said substrate and said gate insulating layer, respectively, at least one of said first and second predetermined depths and said first and second doping densities being selected to change the threshold voltage of said field effect transistor by less than one twentieth of a volt, when the voltage applied to said substrate contact changes by one volt.

Claim 66

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a first doping density; a tub region of second conductivity type in said substrate at said first surface and being doped at a second doping density; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, said channel extending a first predetermined depth from said first surface, said tub region extending a second predetermined depth from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain, substrate and gate contacts for contacting said source and drain regions, said substrate and said gate insulating layer, respectively, at least one of said first and second predetermined depths and said first and second doping densities being selected to change the threshold voltage of said field effect transistor by less than one twentieth of a volt, when the voltage applied to said substrate contact changes by one volt.

Claim 67

The field effect transistor of claim 46 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 68

The field effect transistor of claim 47 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 69

The field effect transistor of claim 48 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.

Claim 70

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a doping density N s , said semiconductor substrate having an intrinsic carrier concentration N i at temperature T degrees Kelvin and a permittivity e s ; a tub region of second conductivity type in said substrate at said first surface and being doped at a doping density which is a factor α times N s ; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, and extending a first predetermined depth Y f from said first surface, said tub region extending a second predetermined depth Y o from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain, substrate and gate contacts for contacting said source and drain regions, said substrate and said gate insulating layer, respectively, said gate contact including a polysilicon layer of said first conductivity type and which is doped at a doping density N p , said first predetermined depth Y f being equal to ##EQU47## where q is equal to 1.6×10 -19 coulombs and K is equal to 1.38×10 -23 Joules/°Kelvin.

Claim 71

A field effect transistor comprising: a semiconductor substrate of first conductivity type, having a first surface and being doped at a doping density N s , said semiconductor substrate having an intrinsic carrier concentration N i at temperature T degrees Kelvin and a permittivity e s ; a tub region of second conductivity type in said substrate at said first surface and being doped at a doping density which is a factor α times N s ; spaced apart source and drain regions of said second conductivity type in said tub region at said first surface; a channel of said second conductivity type in said tub region at said first surface, between said spaced apart source and drain regions, and extending a first predetermined depth Y f from said first surface, said tub region extending a second predetermined depth Y o from said channel; a gate insulating layer on said substrate at said first surface adjacent said channel; and source, drain, substrate and gate contacts for contacting said source and drain regions, said substrate and said gate insulating layer, respectively, said gate contact including a polysilicon layer of said first conductivity type and which is doped at a doping density N p , said first predetermined depth Y f being equal to ##EQU47## where q is equal to 1.6×10 -19 coulombs and K is equal to 1.38×10 -23 Joules/°Kelvin.

Claim 72

The field effect transistor of claim 50 wherein said second predetermined depth Y o is equal to ##EQU48## where φ s is equal to 2φ f +KT/q Lnα, and φ f is the Fermi potential of said semiconductor substrate.

Claim 73

The field effect transistor of claim 50 wherein said source region extends a third predetermined depth from said first surface, and wherein said third predetermined depth is greater than said first predetermined depth and less than the sum of said first and second predetermined depths.

Claim 74

The field effect transistor of claim 52 wherein said source is doped said second conductivity type at a doping concentration which decreases from said first surface to said third predetermined depth.

Claim 75

The field effect transistor of claim 53 wherein said decreasing doping concentration defines a doping center of mass, and wherein said doping center of mass is located at a depth of one half said first predetermined depth.