Field effect transistor

Claim 2

A field effect transistor comprising a semiconductor substrate having a major surface of one conductivity type, source and drain regions of the opposite conductivity type formed in said major surface of said substrate, a channel region in said substrate between said source and drain regions, a single, continuous gate electrode formed above said channel region so as to cover said channel region completely, and a plurality of impurity regions of said opposite conductivity type formed in said channel region under said single, continuous gate electrode with an interval of 0.2 μm or less in the direction of the channel region, each of said impurity regions being separated from said source and drain regions.

Claim 3

A field effect transistor of claim 1, in which said source region, said impurity regions and said drain region are arranged in one direction with each interval of 0.2 μm or less.

Claim 4

A field effect transistor of claim 1, in which the depth of said impurity region ranges from 200 Å to 500 Å.

Claim 5

A field effect transistor of claim 1, in which the length of said impurity region in the direction of said source region to said drain region ranges from 0.02 μm to 0.2 μm.

Claim 6

A field effect transistor of claim 1, in which said impurity region has a impurity density of 10 13 atoms/cm 2 or more.

Claim 7

A field effect transistor comprising a semiconductor substrate, source and drain regions formed in a major surface of said substrate, a channel region positioned between said source and drain regions, a gate insulator film formed on said channel region, a single, continuous gate electrode formed on said gate insulator film so as to cover said channel region completely between said source and drain regions, and a plurality of impurity regions formed in said channel region with an interval of 0.2 μm or less in the direction of said channel region, each of said impurity regions being separated from said source and drain regions, the conductivity type of said impurity regions being the same as that of a channel produced in the surface of portions of said channel region under the operation state of said transistor, said operations of said channel region being free from said impurity regions, and the impurity density of said impurity regions being higher than the carrier density of said channel under said operation state.

Claim 8

A field effect transistor comprising a semiconductor substrate, source and drain regions formed in a major surface of said substrate, a channel region positioned between said source and drain regions, a gate insulator film formed on said channel region, a single, continuous gate electrode formed on said gate insulator film so as to cover said channel region completely between said source and drain regions, and a plurality of impurity regions formed in said channel region with an interval of 0.2 μm or less in the direction of said channel region, each of said impurity regions being separated from said source and drain regions, the conductivity type of said impurity regions being the same as that of a channel produced in the surface of portions of said channel region under the operation state of said transistor, said operations of said channel region being free from said impurity regions, and the impurity density of said impurity regions being higher than the carrier density of said channel under said operation state.

Claim 9

A field effect transistor of claim 6, in which said source region, said impurity regions and said drain region are arranged in one direction with each interval of 0.2 μm or less.

Claim 10

A field effect transistor of claim 6, in which the depth of said impurity region ranges from 200 Å to 500 Å.

Claim 11

A field effect transistor of claim 6, in which the length of said impurity region in the direction of said source region to said drain region ranges from 0.02 μm to 0.2 μm.

Claim 12

A field effect transistor of claim 6, in which said impurity density of said impurity region is 10 13 atoms/cm 2 or more.