Asymmetrical dual-gate FET

Claim 1

A dual gate field effect transistor comprising a semiconductor body of one conductivity type; spaced first, second and third low resistivity regions of the opposite conductivity type lying within said body and adjacent to a common surface of said body, said spaced regions constituting the source, the virtual source-drain and the drain regions respectively, a first conductive channel region being defined by the space between said source and said virtual source-drain; a second channel region being defined by the space between said virtual source-drain and said drain, said second channel region containing a greater concentration of dopant impurities of said opposite type than said first channel region, or said first channel region containing a greater concentration of dopant impurities of said one type than said second channel, or both; an insulating layer covering at least the portions of said surface adjacent to said first and second channels; a first gate electrode on said insulating layer extending over said first channel; a second gate electrode on said insulating layer extending over said second channel; a metal conductor making ohmic connection between an undoped region in said body and said low resistivity source region and being further connected to said second gate electrode; and a protective outer package having first, second and third electrical terminals accessible external to said package, said terminals being connected internal to said package with said source, said first gate electrode and said drain, respectively, such that with a zero bias voltage applied between said first gate and said source, said second channel is more conductive than said first chanNel.