US5675164A
Expired / Lapsed
US
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High performance multi-mesa field effect transistor
Assignee: GlobalFoundries Inc
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Filing: 1995-06-07
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Granted: 1997-10-07
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Expires: 2015-06-07
Abstract
Abstract A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed at sub-lithographic size and pitch as recesses or by epitaxial growth together with exposure of a resist by an interference pattern generation with illuminating radiation and multiple exposures using a mask shifted by a sub-lithographic distance. For an NFET, conduction electron and hole distribution profiles in the mesa structures and gate capacitance are adjusted with dielectric thickness, including deposition of oxide from a liquid solution at room temperature. Transconductance may be altered by change of the aspect ratio of the mesa structures. Lightly doped drain structures are also formed at sub-lithographic sizes by self-aligned processes.
Inventors
- 👤 Timothy A. Brunner
- 👤 Louis L. Hsu
- 👤 Jack A. Mandelman
- 👤 Li-Kong Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:22
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/024; H10D30/60; H10D30/62; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/693; H10P50/695; H10P50/696; H10P76/00; H10P76/20; H10P76/204; G; G03; G03F; G03F7/00; G03F7/20; G03F7/2022; H10D30/601; H10D64/01342; H10D64/01344; H10D64/01346; H10D64/60; H10D64/66; H10D64/68; H10D64/693
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
50 words
A field effect transistor having a conduction region including a plurality of mesa structures, said mesa structures being formed at a pitch of less than one-half micron and a width of less than one-quarter micron by etching and doped to an impurity concentration to operate in a fully depleted mode.
Claim 2
Dependent Claim
50 words
A field effect transistor having a conduction region including a plurality of mesa structures, said mesa structures being formed at a pitch of less than one-half micron and a width of less than one-quarter micron by etching and doped to an impurity concentration to operate in a fully depleted mode.
Claim 3
Dependent Claim
28 words
A field effect transistor as recited in claim 1, including a gated area on at least a portion of at least one side of at least one mesa.
Claim 4
Dependent Claim
23 words
A field effect transistor as recited in claim 1, wherein said plurality of mesa structures are formed by recesses in a semiconductor wafer.
Claim 5
Dependent Claim
20 words
A field effect transistor as recited in claim 1, further including an deposited oxide dielectric only between said mesa structures.
Claim 6
Dependent Claim
19 words
A field effect transistor as recited in claim 4, wherein said oxide dielectric is deposited from liquid phase solution.
Claim 7
Dependent Claim
18 words
A field effect transistor as recited in claim 5, wherein said oxide is deposited at approximately room temperature.
Claim 8
Dependent Claim
21 words
A field effect transistor as recited in claim 6, further including a thermal oxide grown on and between said mesa structures.
Claim 9
Dependent Claim
16 words
A field effect transistor as recited in claim 2, wherein said mesas are epitaxially grown semiconductor.
Claim 10
Dependent Claim
18 words
A field effect transistor as recited in claim 8, further including an oxide dielectric between said mesa structures.
Claim 11
Dependent Claim
21 words
A field effect transistor as recited in claim 9, further including a thermal oxide grown on and between said mesa structures.
Claim 12
Dependent Claim
16 words
A field effect transistor as recited in claim 2, further including a lightly doped drain structure.
Claim 13
Independent Claim
69 words
A method of making a field effect transistor including the steps of exposing a pattern on lines on a lithographic resist, said pattern of lines having a pitch which is less than one-half micron, etching grooves of sub-lithographic width in accordance with said exposure of said resist, forming a grooved surface including mesa structures, forming an oxide on said grooved surface, and applying a gate electrode over said oxide.
Claim 14
Independent Claim
69 words
A method of making a field effect transistor including the steps of exposing a pattern on lines on a lithographic resist, said pattern of lines having a pitch which is less than one-half micron, etching grooves of sub-lithographic width in accordance with said exposure of said resist, forming a grooved surface including mesa structures, forming an oxide on said grooved surface, and applying a gate electrode over said oxide.
Claim 15
Dependent Claim
28 words
A method as recited in claim 12, wherein said pattern of lines has a pitch which is less than a wavelength of radiation used for said exposure step.
Claim 16
Dependent Claim
19 words
A method as recited in claim 12, including the further step of depositing a dielectric between said mesa structures.
Claim 17
Dependent Claim
13 words
A method as recited in claim 14, wherein said dielectric is an oxide.
Claim 18
Dependent Claim
16 words
A method as recited in claim 15, wherein said oxide is deposited from liquid phase solution.
Claim 19
Dependent Claim
16 words
A method as recited in claim 16, wherein said depositing step is performed at room temperature.
Claim 20
Dependent Claim
20 words
A method as recited in claim 12, including the further step of forming a thermal oxide on said grooved surface.
Claim 21
Dependent Claim
20 words
A method as recited in claim 17, including the further step of forming a thermal oxide on said grooved surface.
Claim 22
Dependent Claim
71 words
A method as recited in claim 12, wherein said exposing step includes the steps of depositing a layer of material prior to said resist, making a first lithographic exposure of said resist through a lithographic mask, shifting said mask by a sub-lithographic distance, and making a second lithographic exposure of said resist, and including the further step of etching said layer of material in accordance with said first and second exposures.
Claim 23
Dependent Claim
42 words
A method as recited in claim 20, comprising the further steps of forming sidewalls on remaining portions of said material, removing said portion of said layer of material to form a mask, and performing said etching step in accordance with said mask.
Claim 24
Dependent Claim
22 words
A method as recited in claim 12, wherein said exposing step includes the step of forming an interference pattern with said radiation.
Claim 25
Dependent Claim
19 words
A method as recited in claim 22, wherein said interference pattern is developed with a strong phase shift mask.
Claim 26
Dependent Claim
20 words
A method as recited in claim 22, wherein said interference pattern is derived by off-axis illumination through a grating pattern.
Claim 27
Dependent Claim
38 words
A method as recited in claim 22, wherein said interference pattern is derived by illuminating said resist from two radiation sources having the same radiation wavelength and having said radiation directed at said resist from a shallow angle.
Claim 28
Dependent Claim
37 words
A semiconductor wafer having a region of a surface patterned with a plurality of elongated features which have a width less than or equal to one-quarter micron and a pitch less than or equal to one-half micron.
Claim 29
Dependent Claim
37 words
A semiconductor wafer having a region of a surface patterned with a plurality of elongated features which have a width less than or equal to one-quarter micron and a pitch less than or equal to one-half micron.
Claim 30
Independent Claim
60 words
A method of making a semiconductor wafer including the steps of depositing a layer of material, depositing a resist, making a first lithographic exposure of said resist through a lithographic mask, shifting said mask by a sub-lithographic distance, making a second lithographic exposure of said resist, and etching said layer of material in accordance with said first and second exposures.
Claim 31
Independent Claim
60 words
A method of making a semiconductor wafer including the steps of depositing a layer of material, depositing a resist, making a first lithographic exposure of said resist through a lithographic mask, shifting said mask by a sub-lithographic distance, making a second lithographic exposure of said resist, and etching said layer of material in accordance with said first and second exposures.
Claim 32
Independent Claim
54 words
A method of making a semiconductor wafer including the steps of applying a resist to a surface of said semiconductor wafer, exposing said resist with a pattern of radiation to form a pattern of elongated features at a pitch which is less than one-half micron, and etching said surface in accordance with said pattern.
Claim 33
Independent Claim
54 words
A method of making a semiconductor wafer including the steps of applying a resist to a surface of said semiconductor wafer, exposing said resist with a pattern of radiation to form a pattern of elongated features at a pitch which is less than one-half micron, and etching said surface in accordance with said pattern.
Claim 34
Dependent Claim
35 words
A method as recited in claim 28, wherein said exposing step includes the further step of forming an interference pattern of said radiation such that said pitch is less than a wavelength of said radiation.
Claim 35
Dependent Claim
19 words
A method as recited in claim 29, wherein said interference pattern is developed with a strong phase shift mask.
Claim 36
Dependent Claim
20 words
A method as recited in claim 29, wherein said interference pattern is derived by off-axis illumination through a grating pattern.
Claim 37
Dependent Claim
38 words
A method as recited in claim 29, wherein said interference pattern is derived by illuminating said resist from two radiation sources having the same radiation wavelength and having said radiation directed at said resist from a shallow angle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |