Patent US7065481B2 successfully refreshed from Google Patents.
US7065481B2
Expired / Lapsed
US
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Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
Assignee: Synopsys Inc
•
Filing: 2002-07-31
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Granted: 2006-06-20
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Expires: 2022-07-31
Abstract
Abstract Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
Inventors
- 👤 Nils Endric Schubert
- 👤 John Mark Beardslee
- 👤 Gernot Heinrich Koch
- 👤 Olaf Poeppe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:41
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/318364; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
141 words
A method for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said method comprising: (a) activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry; (b) determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; (c) configuring the instrumentation circuitry in accordance with the configuration information; (d) configuring the instrumentation circuitry to interoperate with the at least one logic analyzer; (e) receiving debug data from the configured instrumentation circuitry operating within the electronic system product; (f) translating the debug data into HDL-related debug information; and (g) relating the HDL-related debug information to the HDL description.
Claim 2
Independent Claim
141 words
A method for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said method comprising: (a) activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry; (b) determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; (c) configuring the instrumentation circuitry in accordance with the configuration information; (d) configuring the instrumentation circuitry to interoperate with the at least one logic analyzer; (e) receiving debug data from the configured instrumentation circuitry operating within the electronic system product; (f) translating the debug data into HDL-related debug information; and (g) relating the HDL-related debug information to the HDL description.
Claim 3
Dependent Claim
32 words
A method as recited in claim 1 , wherein at least a portion of the debug data being received from the configured instrumentation circuitry is from the at least one logic analyzer.
Claim 4
Dependent Claim
31 words
A method as recited in claim 1 , wherein at least a portion of the design patching aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 5
Dependent Claim
34 words
A method as recited in claim 1 , wherein at least a portion of the design visibility or design control aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 6
Dependent Claim
44 words
A method as recited in claim 4 , wherein said method further comprises: (h) configuring the at least one logic analyzer based on the portion of the design visibility or design control aspects of the instrumentation circuitry to be performed by the logic analyzer.
Claim 7
Dependent Claim
22 words
A method as recited in claim 5 , wherein said configuring (c) and said configuring (h) are automatically performed without user interaction.
Claim 8
Dependent Claim
36 words
A method as recited in claim 5 , wherein the design visibility comprises sampling performed by the at least one logic analyzer and the design control comprises triggering performed by the at least one logic analyzer.
Claim 9
Dependent Claim
32 words
A method as recited in claim 5 , wherein at least a portion of the debug data being received from the configured instrumentation circuitry is from the at least one logic analyzer.
Claim 10
Dependent Claim
31 words
A method as recited in claim 8 , wherein at least a portion of the design patching aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 11
Dependent Claim
25 words
A method as recited in claim 1 , wherein said method further comprises: (h) displaying the HDL description with the HDL-related debug information related thereto.
Claim 12
Dependent Claim
29 words
A method as recited in claim 10 , wherein said displaying (h) operates to display the HDL-related debug information as visual indicators on the HDL-related debug information being displayed.
Claim 13
Dependent Claim
14 words
A method as recited in claim 11 , wherein the visual indicators are tags.
Claim 14
Dependent Claim
31 words
A method as recited in claim 10 , wherein at least a portion of the design patching aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 15
Dependent Claim
32 words
A method as recited in claim 13 , wherein at least a portion of the debug data being received from the configured instrumentation circuitry is from the at least one logic analyzer.
Claim 16
Dependent Claim
34 words
A method as recited in claim 13 , wherein at least a portion of the design visibility or design control aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 17
Dependent Claim
173 words
A computer readable storage medium including at least computer program code for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said computer readable medium comprising: computer program code for activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry; computer program code for determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; computer program code for configuring the instrumentation circuitry in accordance with the configuration information; computer program code for configuring the instrumentation circuitry to interoperate with the at least one logic analyzer; computer program code for receiving debug data from the configured instrumentation circuitry operating within the electronic system product; computer program code for translating the debug data into HDL-related debug information; and computer program code for relating the HDL-related debug information to the HDL description.
Claim 18
Dependent Claim
173 words
A computer readable storage medium including at least computer program code for debugging an electronic system having instrumentation circuitry included therein, the electronic system being coupled to at least one logic analyzer, wherein the electronic system is described with a HDL, said computer readable medium comprising: computer program code for activating certain design visibility, design patching or design control aspects of the instrumentation circuitry available for examining or modifying the electronic system via the instrumentation circuitry; computer program code for determining configuration information based on the certain design visibility, design patching or design control aspects that are activated; computer program code for configuring the instrumentation circuitry in accordance with the configuration information; computer program code for configuring the instrumentation circuitry to interoperate with the at least one logic analyzer; computer program code for receiving debug data from the configured instrumentation circuitry operating within the electronic system product; computer program code for translating the debug data into HDL-related debug information; and computer program code for relating the HDL-related debug information to the HDL description.
Claim 19
Dependent Claim
35 words
A computer storage readable medium as recited in claim 16 , wherein at least a portion of the debug data being received from the configured instrumentation circuitry is from the at least one logic analyzer.
Claim 20
Dependent Claim
33 words
A computer readable medium as recited in claim 16 , wherein at least a portion of the design patching aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 21
Dependent Claim
36 words
A computer readable medium as recited in claim 16 , wherein at least a portion of the design visibility or design control aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 22
Dependent Claim
51 words
A computer readable storage medium as recited in claim 19 , wherein said computer readable medium further comprises: computer program code for configuring the at least one logic analyzer based on the portion of design visibility or design control aspects of the instrumentation circuitry to be performed by the logic analyzer.
Claim 23
Dependent Claim
40 words
A computer readable storage medium as recited in claim 20 , wherein said computer program code for configuring the instrumentation circuitry and said computer program code for configuring the at least one logic analyzer are automatically performed without user interaction.
Claim 24
Dependent Claim
38 words
A computer readable medium as recited in claim 20 , wherein the design visibility comprises sampling performed by the at least one logic analyzer and the design control comprises triggering performed by the at least one logic analyzer.
Claim 25
Dependent Claim
34 words
A computer readable medium as recited in claim 20 , wherein at least a portion of the debug data being received from the configured instrumentation circuitry is from the at least one logic analyzer.
Claim 26
Dependent Claim
34 words
A computer readable storage medium as recited in claim 23 , wherein at least a portion of the design patching aspects of the instrumentation circuitry are performed by the at least one logic analyzer.
Claim 27
Dependent Claim
33 words
A computer readable storage medium as recited in claim 16 , wherein said computer readable medium further comprises: computer program code for displaying the HDL description with the HDL-related debug information related thereto.
Claim 28
Dependent Claim
35 words
A computer readable storage medium as recited in claim 25 , wherein said computer program code for displaying operates to display the HDL-related debug information as visual indicators on the HDL-related debug information being displayed.
Claim 29
Dependent Claim
17 words
A computer readable storage medium as recited in claim 26 , wherein the visual indicators are tags.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-06-19 | 2009-12-19 | 2010-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-06-19 | 2013-12-19 | 2014-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-06-19 | 2017-12-19 | 2018-06-20 | $7700.00 | Window Closed / Lapsed |