US5933356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
Assignee: LSI Corp
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Filing: 1996-11-05
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Granted: 1999-08-03
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Expires: 2016-11-05
Abstract
Abstract A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.
Inventors
- 👤 Michael D. Rostoker
- 👤 Carlos Dangelo
- 👤 Owen S. Bair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/31704; G01R31/318364; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
94 words
An ECAD system for creating and validating a structural description of a circuit or device from a VHDL description of the circuit or device, comprising: a compiler for compiling the VHDL description of the circuit or device; means for locating problems within said compiled description and measuring the effectiveness of solving said problems; means for passing information including said compiled description to a physical design level; a physical design tool for receiving said information and creating a physical design therefrom; and means for back annotating information from the physical design tool to the compiler.
Claim 2
Dependent Claim
94 words
An ECAD system for creating and validating a structural description of a circuit or device from a VHDL description of the circuit or device, comprising: a compiler for compiling the VHDL description of the circuit or device; means for locating problems within said compiled description and measuring the effectiveness of solving said problems; means for passing information including said compiled description to a physical design level; a physical design tool for receiving said information and creating a physical design therefrom; and means for back annotating information from the physical design tool to the compiler.
Claim 3
Dependent Claim
22 words
The system of claim 1, wherein said information received by said physical design tool comprises timing information relating to the physical design.
Claim 4
Dependent Claim
20 words
The system of claim 1, further comprising a verification tool to verify design choices made by said physical design tool.
Claim 5
Dependent Claim
15 words
The system of claim 1, further comprising a simulation tool to simulate design description functionality.
Claim 6
Dependent Claim
80 words
A constraint analyzer for use in a system for creating and validating a structural device or circuit in a multi-windowing graphical user interface (GUI) environment, comprising: means for receiving library data and a gate-level netlist; means for receiving information including a VHDL representation of the device or circuit; and a gate level power analysis tool for exploring device or circuit power design tradeoffs based on library data, the gate level netlist, and the VHDL representation of the circuit or device.
Claim 7
Dependent Claim
80 words
A constraint analyzer for use in a system for creating and validating a structural device or circuit in a multi-windowing graphical user interface (GUI) environment, comprising: means for receiving library data and a gate-level netlist; means for receiving information including a VHDL representation of the device or circuit; and a gate level power analysis tool for exploring device or circuit power design tradeoffs based on library data, the gate level netlist, and the VHDL representation of the circuit or device.
Claim 8
Dependent Claim
61 words
A compiling tool for use in a system for creating and validating a structural device or circuit in a multi-windowing graphical user interface (GUI) environment, comprising: means for receiving predetermined device or circuit parameters; and a synthesizing element for synthesizing circuits by simultaneously optimizing predetermined constraints based on said predetermined parameters and creating a constraint optimized gate-level netlist of said circuits.
Claim 9
Dependent Claim
61 words
A compiling tool for use in a system for creating and validating a structural device or circuit in a multi-windowing graphical user interface (GUI) environment, comprising: means for receiving predetermined device or circuit parameters; and a synthesizing element for synthesizing circuits by simultaneously optimizing predetermined constraints based on said predetermined parameters and creating a constraint optimized gate-level netlist of said circuits.
Claim 10
Dependent Claim
22 words
The compiling tool of claim 6, wherein said predetermined constraints comprise at least one from the group of timing, area, and power.
Claim 11
Independent Claim
82 words
A method for creating and validating a structural description of a circuit or device from a VHDL description of the circuit or device, comprising the steps of: compiling the VHDL description of the circuit or device; locating problems within said compiled description and measuring the effectiveness of solving said problems; passing information including said compiled description to a physical design level; receiving said information and creating a physic design therefrom; and back annotating information from the physical design tool to the compiler.
Claim 12
Independent Claim
82 words
A method for creating and validating a structural description of a circuit or device from a VHDL description of the circuit or device, comprising the steps of: compiling the VHDL description of the circuit or device; locating problems within said compiled description and measuring the effectiveness of solving said problems; passing information including said compiled description to a physical design level; receiving said information and creating a physic design therefrom; and back annotating information from the physical design tool to the compiler.
Claim 13
Dependent Claim
23 words
The method of claim 8, wherein said information received by said receiving and creating step comprises timing information relating to the physical design.
Claim 14
Dependent Claim
17 words
The method of claim 8, further comprising verifying design choices made by said receiving and creating step.
Claim 15
Dependent Claim
11 words
The method of claim 10, further comprising simulating design description functionality.
Claim 16
Independent Claim
71 words
A method of creating and validating an electronic design from a behavioral description thereof, comprising the steps of: providing a behavioral description of the electronic design; simulating and changing the behavioral description of the design; partitioning the behavioral description into a number of blocks and constraining the architectural choices to those meeting high-level timing goals; and creating a physical design by iteratively feeding back physical design characteristics to the behavioral level.
Claim 17
Independent Claim
71 words
A method of creating and validating an electronic design from a behavioral description thereof, comprising the steps of: providing a behavioral description of the electronic design; simulating and changing the behavioral description of the design; partitioning the behavioral description into a number of blocks and constraining the architectural choices to those meeting high-level timing goals; and creating a physical design by iteratively feeding back physical design characteristics to the behavioral level.
Claim 18
Independent Claim
72 words
A system for creating and validating an electronic design from a behavioral description thereof, comprising: a simulation tool for simulating and changing the behavioral description of the design; a partitioning tool for partitioning the behavioral description into a number of blocks and constraining the architectural choices to those meeting high-level timing goals; and a physical design tool creating a physical design by iteratively feeding back physical design characteristics to the behavioral level.
Claim 19
Independent Claim
72 words
A system for creating and validating an electronic design from a behavioral description thereof, comprising: a simulation tool for simulating and changing the behavioral description of the design; a partitioning tool for partitioning the behavioral description into a number of blocks and constraining the architectural choices to those meeting high-level timing goals; and a physical design tool creating a physical design by iteratively feeding back physical design characteristics to the behavioral level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |