EP0463301A2
Expired / Lapsed
EP
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Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
Assignee: LSI Corp
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Filing: 1991-04-05
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Granted: —
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Expires: 2011-04-05
Abstract
Abstract A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics inbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.
Inventors
- 👤 Carlos Dangelo
- 👤 Vijay Kumar Nagasamy
- 👤 Ahsan Bootehsaz
- 👤 Sreeranga Prasannakumar Rajan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 22:44
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31704; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
98 words
A method of creating and validating a structural description of a circuit or device from a higher level, behavior-oriented description thereof, comprising: specifying a design far desired behavior of a circuit or device, including high-level timing goals, in a high-level, behavior-oriented language; iteratively simulating and changing the design at the behavioral-level until the desired behavior is obtained; partitioning the design into a number of architectural blocks; constraining the architectural choices to those which meet the high-level timing goals; and directing the various architectural blocks to logic synthesis programs, thereby providing a netlist or gate-level description of the design.
Claim 2
Dependent Claim
45 words
A method according to claim 1, wherein: architectural blocks having highly regular structures or well understood functions are directed to specific logic synthesis programs (e.g. memory or function compilers); and architectural blocks with random or unstructured logic are directed to more general logic synthesis programs.
Claim 3
Dependent Claim
43 words
A method according to claim 1, further comprising: simulating the gate-level design description; and comparing the results of the gate-level simulation with those from the behavioral simulation to ensure that the circuit implementation behaves as intended and that the timing goals are achieved.
Claim 4
Dependent Claim
25 words
A method according to claim 3, further comprising: back-annotating the design to ensure that other physical design limitations, such as capacitive loads, are not exceeded.
Claim 5
Dependent Claim
29 words
A method according to claim 3, further comprising: inputting the net list or gate-level description of the design to a system for creating the physical implementation of the design.
Claim 6
Dependent Claim
29 words
A method according to claim 1, further comprising: an intermediate step, between the behavioral and net-list descriptions of the design, of describing the design at the register transfer level.
Claim 7
Dependent Claim
25 words
A method according to claim 1, wherein: the intent and meaning present in the behavioral description is preserved at the net list or gate-level description.
Claim 8
Dependent Claim
47 words
A method according to claim 1, further comprising: in the partitioning step, providing high-level timing information extracted from known chip floorplan parameters to constrain the design into the feasible architectural choices which meet the high-level timing goals, thereby allowing the process to converge to specific physical embodiments.
Claim 9
Dependent Claim
26 words
A method according to claim 8, further comprising: extracting timing data from floorplan parameters; and incorporating this data into I/O ports of the high-level behavioral description.
Claim 10
Dependent Claim
19 words
A method according to claim 1, wherein the high-level behavioral description of the device is set forth in VHDL.
Claim 11
Dependent Claim
32 words
A method according to claim 1, further comprising: interpreting the behavioral description of the device by attaching one or more semantic rules to each of the syntactic rules underlying the behavioral description.
Claim 12
Dependent Claim
17 words
A method according to claim 11, wherein the interpreting is accomplished by using a "syntax attribute tree".
Claim 13
Independent Claim
84 words
A method of deriving a structural description of a system from a behavioral description thereof, comprising: (a) specifying a behavioral design for a system in a high-level, behavior-oriented language; (b) describing, in the high-level language, a functional description of the design of the system; (c) partitioning the functional description into a number of architectural blocks; (d) constraining the architectural choices for the design to those which meet the desired behavior; and (e) mapping the architecturally constrained design into a structural description of the system.
Claim 14
Dependent Claim
43 words
A method according to claim 13, further comprising: between the steps (b) and (c), verifying, in the high-level language, for correctness of intended functionality and, if necessary, iteratively simulating and changing the functional description of the system until the desired functionality is obtained.
Claim 15
Dependent Claim
35 words
A method according to claim 13, further comprising: between the steps (d) and (e), composing the architectural choices as a structural description of the system; and verifying the architectural decisions that were made during partitioning.
Claim 16
Dependent Claim
24 words
A method according to claim 13, further comprising: after the step (e), verifying the correctness of the of the structural description of the system.
Claim 17
Independent Claim
73 words
A method of creating and validating a structural description of a device from a behavior-oriented description, comprising: specifying a behavioral description for a desired behavior of a device in a high-level, behavior-oriented language; iteratively simulating and changing the behavioral description until the desired behavior is obtained; partitioning the behavioral description into architectural blocks; synthesizing a structural description of the architectural blocks in a lower-level language; and simulating the functionality of the structural description.
Claim 18
Independent Claim
14 words
A method according to claims 17, wherein: the device is a circuit or system.
Claim 19
Dependent Claim
39 words
A method according to claim 17, wherein: the device is a design entity; and the design entity is an entire system, a sub-system, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between.
Claim 20
Dependent Claim
12 words
A method according to claim 17, further comprising: implementing the structural description.
Claim 21
Independent Claim
77 words
A method of partitioning the design of a digital device, comprising: partitioning a design into functional blocks; generally laying out the partitioned design; selecting existing designs for a portion of the functional blocks; generating another portion of the functional blocks; partitioning yet another portion of the functional blocks into smaller functional units; synthesizing the remaining portion of the functional blocks; generating a structural description of the functional blocks and units; predicting delays between functional blocks and units;
Claim 22
Dependent Claim
15 words
A method according to claim 21, further comprising: back-annotating the delays to provide timing optimization;
Claim 23
Dependent Claim
18 words
A method according to claim 21, further comprising: using the delays to derive boundary constraints for timing optimization.
References Cited (Backward Citations)
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