US5822564A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Checkpointing in an emulation system
Assignee: Cadence Design Systems Inc
•
Filing: 1996-06-28
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Granted: 1998-10-13
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Expires: 2016-06-28
Abstract
Abstract A method and apparatus for outputting a current state of a real-time circuit emulator. When the emulator is set to a predetermined state, it checkpoints the contents of certain memory and registers at the time it enters the predetermined state. The output of the emulator can be used as input to the emulator or as input to another system, such as a simulator, which does not operate in real-time. If the simulator also generates an output having same format, the output of the simulator can also be input to the real-time emulator.
Inventors
- 👤 John Chilton
- 👤 Tony Sarno
- 👤 Ingo Schaefer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G06F11/36; G06F11/362; G06F11/3648; G06F11/3652
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
208 words
An apparatus for emulating a circuit in real-time, the apparatus including a logic processor for solving equations to emulate the circuit design, wherein the logic processor has logic processor inputs and logic processor outputs, comprising: a first selector having first selector inputs and first selector outputs, wherein one or more outputs from the logic processor are coupled to the first selector inputs, wherein the first selector selects a subset of signals at the first selector inputs and applies the selected signals to the first selector outputs; a register having register inputs and register outputs, wherein the register inputs are coupled to the outputs of the first selector, wherein the register stores the signals received from the first selector; a second selector having second selector inputs and second selector outputs, wherein the second selector inputs are coupled to the register outputs for selectively applying the register outputs to the second selector outputs; wherein the inputs of the logic processor are coupled to the output of the second selector; and an input line, having a first state indicating that the emulator is in SCAN mode; an output portion, coupled to the register and the input line, for outputting the contents of the register when input line enters the first state.
Claim 2
Independent Claim
208 words
An apparatus for emulating a circuit in real-time, the apparatus including a logic processor for solving equations to emulate the circuit design, wherein the logic processor has logic processor inputs and logic processor outputs, comprising: a first selector having first selector inputs and first selector outputs, wherein one or more outputs from the logic processor are coupled to the first selector inputs, wherein the first selector selects a subset of signals at the first selector inputs and applies the selected signals to the first selector outputs; a register having register inputs and register outputs, wherein the register inputs are coupled to the outputs of the first selector, wherein the register stores the signals received from the first selector; a second selector having second selector inputs and second selector outputs, wherein the second selector inputs are coupled to the register outputs for selectively applying the register outputs to the second selector outputs; wherein the inputs of the logic processor are coupled to the output of the second selector; and an input line, having a first state indicating that the emulator is in SCAN mode; an output portion, coupled to the register and the input line, for outputting the contents of the register when input line enters the first state.
Claim 3
Dependent Claim
41 words
The apparatus of claim 1, further comprising: a memory coupled to the logic processor; and an output portion, coupled to the memory and the input line, for outputting the contents of the memory when the input line enters the first state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |