US5068812A
Expired / Lapsed
US
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Event-controlled LCC stimulation
Assignee: Philips Semiconductors Inc
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Filing: 1989-07-18
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Granted: 1991-11-26
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Expires: 2009-07-18
Abstract
Abstract A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluated. A second list is formed of each component and its corresponding output signals. The external input signals are also listed. Each external input signal is tested for change from a previous evaluation and, if so, the corresponding components in the re-evaluation list are marked for reevaluation. Each component, in levelized order, is then tested to determine whether that component is marked for re-evaluation and, if so, that component is re-evaluated and unmarked, and each signal in the component output signal list which has a non-empty re-evaluation list is tested to determine if the value of the signal has changed since the previous evaluation and, if so, all of the components in that signal's reevaluation list are marked for re-evaluation. Evaluation marks are stored as a marking bit in a memory location associated with a component. The components associated with frequently changing input signals are evaluated without setting or testing their evaluation marks. All reevaluation marks are cleared at the beginning of the execution of the simulation.
Inventors
- 👤 Thomas J. Schaefer
- 👤 Robert D. Shur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:30
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
252 words
A method of simulating operation of a levelized logic circuit, said method comprising the steps of: storing in a computer memory data representing a specified logic circuit, said logic circuit having a number of nodes between which are connected circuit components, each of said nodes having a signal present thereat with the value of said signal indicating the state of said node; said stored logic circuit data including an assigned logic level for each circuit component; computing a storing in said computer memory a set of evaluation lists, each said evaluation list corresponding to a signal and denoting those components that are to be evaluated when said signal changes value; computing and storing in said computer memory an output signal list denoting output signals corresponding to each component of said logic circuit; computing and storing in said computer memory a list of external input signals to the logic circuit; whenever an external input signal changes value, storing an evaluation mark for each component in said external input signal's evaluation list; and for each component, in levelized order, for which an evaluation mark has been stored; evaluating the component; clearing the evaluation mark for the component; and for each signal in the output signal list corresponding to said evaluated component which has a nonempty evaluation list, (A) determining whether the value of the signal was changed by said evaluating step; and (B) if the value of the signal has changed, storing evaluation marks for all of the components in that signal's evaluation list.
Claim 2
Independent Claim
252 words
A method of simulating operation of a levelized logic circuit, said method comprising the steps of: storing in a computer memory data representing a specified logic circuit, said logic circuit having a number of nodes between which are connected circuit components, each of said nodes having a signal present thereat with the value of said signal indicating the state of said node; said stored logic circuit data including an assigned logic level for each circuit component; computing a storing in said computer memory a set of evaluation lists, each said evaluation list corresponding to a signal and denoting those components that are to be evaluated when said signal changes value; computing and storing in said computer memory an output signal list denoting output signals corresponding to each component of said logic circuit; computing and storing in said computer memory a list of external input signals to the logic circuit; whenever an external input signal changes value, storing an evaluation mark for each component in said external input signal's evaluation list; and for each component, in levelized order, for which an evaluation mark has been stored; evaluating the component; clearing the evaluation mark for the component; and for each signal in the output signal list corresponding to said evaluated component which has a nonempty evaluation list, (A) determining whether the value of the signal was changed by said evaluating step; and (B) if the value of the signal has changed, storing evaluation marks for all of the components in that signal's evaluation list.
Claim 3
Dependent Claim
27 words
The method of claim 1 including the step of clearing all of the evaluation marks for all of the components at the beginning of each circuit evaluation.
Claim 4
Dependent Claim
27 words
THe method of claim 1 including the step of clearing all of the evaluation marks for all of the components at the end of each circuit simulation.
Claim 5
Dependent Claim
29 words
The method of claim 1 including the step of evaluating components associated with input signals that change frequently without determining whether the value of said input signals have changed.
Claim 6
Independent Claim
297 words
A method of automatically generating program instructions for a compiled computer program, which is used for simulating a levelized logic circuit, said method of automatically generating program instructions comprising the steps of: (5-1) generating program instructions for: (A) storing in a computer memory data representing a specified logic circuit, said logic circuit having a number of nodes between which are connected circuit components, each of said nodes having a signal present thereat with the value of said signal indicating the state of said node; said stored logic circuit data including an assigned logic level for each circuit component; (B) computing and storing in said computer memory a set of evaluation lists, each said evaluation list corresponding to a signal and denoting those components that are to be evaluated when said signal changed value; (C) computing and storing in said computer memory an output signal is denoting output signals corresponding to each component of said logic circuit; (D) computing and storing in said computer memory a list of external input signals to the logic circuit; (E) whenever an external input signal changes value, storing an evaluation mark for each component in said external input signal's evaluation list; and (F) for each component, in levelized order, for which an evaluation mark has been stored: evaluating the component; clearing the evaluation mark for the component; and for each signal in the output signal list corresponding to said evaluated component which has a non-empty evaluation list, (A) determining whether the value of the signal was changed by said evaluating step; and (B) if the value of the signal has changed, storing evaluation marks for all of the components in that signal's evaluation list; and (5-2) compiling said generated program instructions into a compiled computer program for simulating said specified logic circuit.
Claim 7
Independent Claim
297 words
A method of automatically generating program instructions for a compiled computer program, which is used for simulating a levelized logic circuit, said method of automatically generating program instructions comprising the steps of: (5-1) generating program instructions for: (A) storing in a computer memory data representing a specified logic circuit, said logic circuit having a number of nodes between which are connected circuit components, each of said nodes having a signal present thereat with the value of said signal indicating the state of said node; said stored logic circuit data including an assigned logic level for each circuit component; (B) computing and storing in said computer memory a set of evaluation lists, each said evaluation list corresponding to a signal and denoting those components that are to be evaluated when said signal changed value; (C) computing and storing in said computer memory an output signal is denoting output signals corresponding to each component of said logic circuit; (D) computing and storing in said computer memory a list of external input signals to the logic circuit; (E) whenever an external input signal changes value, storing an evaluation mark for each component in said external input signal's evaluation list; and (F) for each component, in levelized order, for which an evaluation mark has been stored: evaluating the component; clearing the evaluation mark for the component; and for each signal in the output signal list corresponding to said evaluated component which has a non-empty evaluation list, (A) determining whether the value of the signal was changed by said evaluating step; and (B) if the value of the signal has changed, storing evaluation marks for all of the components in that signal's evaluation list; and (5-2) compiling said generated program instructions into a compiled computer program for simulating said specified logic circuit.
Claim 8
Dependent Claim
25 words
The method of claim 5, including the step of generating program instructions for clearing all said evaluation marks at the beginning of each circuit evaluation.
Claim 9
Dependent Claim
34 words
The method of claim 5, including the step of generating program instructions for automatically evaluating components associated with input signals that change frequently without determining whether the value of said input signals have changed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |