US5754827A
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Method and apparatus for performing fully visible tracing of an emulation
Assignee: Mentor Graphics Corp
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Filing: 1995-10-13
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Granted: 1998-05-19
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Expires: 2015-10-13
Abstract
Abstract An emulation system is constituted with a plurality of FPGAs having on-chip integrated debugging facilities, distributively disposed on a plurality of circuit boards. Each FPGA's on-chip integrated debugging facilities include in particular, a scan register for outputting trace data, and comparison circuitry for generating inputs for a plurality of system triggers. Correspondingly, each board is provided with a plurality of trace memory for recording the trace data, and summing circuitry for generating partial sums for the triggers. The relative memory location within a clock cycle of trace data where the output of a LE will be recorded is predeterminable. Additionally, a system sync memory is provided for storing a plurality of sync patterns to facilitate reconstitution of trace data of a trace session. Lastly, the compilation or mapping software is enhanced to generate a cross-reference file cross referencing each circuit element in a circuit design to the predeterminable relative memory location within a clock cycle of trace data where the trace data for the particular circuit element can be found. Together, these elements allow fully visible tracing to be performed for an emulation.
Inventors
- 👤 Jean Barbier
- 👤 Olivier LePape
- 👤 Frederic Reblewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G01R31/318591; G06F11/22; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
130 words
An apparatus comprising: a plurality of field programmable gate arrays (FPGAs) for emulating at least a subset of a circuit design, each field programmable gate array being a single integrated circuit comprising both a plurality of logic elements (LEs) for realizing circuit elements of the at least a subset of the circuit design and a first on-chip integrated debugging facility for outputting signal state values of the LEs on a clock cycle by clock cycle basis; and trace memory coupled to the FPGAs comprising a plurality of memory locations for capturing and storing the LE signal state values output in a deterministic locality topology, under which the relative memory location within a clock cycle of trace data where the signal state value of a circuit element is stored is predeterminable.
Claim 2
Independent Claim
130 words
An apparatus comprising: a plurality of field programmable gate arrays (FPGAs) for emulating at least a subset of a circuit design, each field programmable gate array being a single integrated circuit comprising both a plurality of logic elements (LEs) for realizing circuit elements of the at least a subset of the circuit design and a first on-chip integrated debugging facility for outputting signal state values of the LEs on a clock cycle by clock cycle basis; and trace memory coupled to the FPGAs comprising a plurality of memory locations for capturing and storing the LE signal state values output in a deterministic locality topology, under which the relative memory location within a clock cycle of trace data where the signal state value of a circuit element is stored is predeterminable.
Claim 3
Dependent Claim
73 words
The apparatus as set forth in claim 1, wherein the trace memory comprises a plurality of trace memory units correspondingly coupled to the FPGAs, each trace memory unit comprises memory locations for storing N clock cycles of LE signal state values, and the signal state value of a LE is stored in a predetermined fixed offset into each block of memory locations used for storing a clock cycle of LE signal state values.
Claim 4
Dependent Claim
43 words
The apparatus as set forth in claim 1, wherein the apparatus further comprises an address counter coupled to the trace memory units for generating addresses for the trace memory units in a manner coordinated with the outputting of the LE signal state values.
Claim 5
Dependent Claim
66 words
The apparatus as set forth in claim 1, wherein each FPGA further comprises a second on-chip integrated debugging facility for outputting the LE signal state values as inputs to at least one trigger; and the apparatus further comprises at least one summing circuit coupled to the FPGAs for generating a partial sum of the LE signal state values for each of the at least one trigger.
Claim 6
Independent Claim
122 words
An apparatus comprising: a plurality of field programmable gate arrays (FPGAs) for emulating a circuit design, each field programmable gate array being a single integrated circuit comprising both a plurality of combinatorial logic blocks (LEs) for realizing circuit elements of the circuit design and a first on-chip integrated debugging facility for outputting signal state values of the LEs on a clock cycle by clock cycle basis; and trace memory coupled to the FPGAs comprising a plurality of memory locations for capturing and storing the LE signal state values output in a deterministic locality topology, under which the relative memory location within a clock cycle of LE signal state values where the signal state value of a particular LE is stored is predeterminable.
Claim 7
Independent Claim
122 words
An apparatus comprising: a plurality of field programmable gate arrays (FPGAs) for emulating a circuit design, each field programmable gate array being a single integrated circuit comprising both a plurality of combinatorial logic blocks (LEs) for realizing circuit elements of the circuit design and a first on-chip integrated debugging facility for outputting signal state values of the LEs on a clock cycle by clock cycle basis; and trace memory coupled to the FPGAs comprising a plurality of memory locations for capturing and storing the LE signal state values output in a deterministic locality topology, under which the relative memory location within a clock cycle of LE signal state values where the signal state value of a particular LE is stored is predeterminable.
Claim 8
Dependent Claim
53 words
The apparatus as set forth in claim 5, wherein, the FPGAs are distributively disposed in a plurality of logic boards, and the trace memory comprises a plurality of trace memory units correspondingly coupled to the FPGAs, one trace memory unit per FPGA, and disposed on the same logic board with the coupled FPGA.
Claim 9
Dependent Claim
57 words
The apparatus as set forth in claim 6, wherein each trace memory unit comprises memory locations for storing N clock cycles of LE signal state values, and the signal state value of a LE is stored in a predetermined fixed offset into each block of memory locations for storing a clock cycle of LE signal state values.
Claim 10
Dependent Claim
59 words
The apparatus as set forth in claim 7, wherein the apparatus further comprises a plurality of address counters correspondingly disposed on the logic boards and coupled to the trace memory units of the same logic board for locally generating addresses for the local trace memory units in a manner coordinated with the outputting of the LE signal state values.
Claim 11
Dependent Claim
52 words
The apparatus as set forth in claim 7, wherein the trace data are stored into the trace memory units in a wrap around manner, and the apparatus further comprises a system sync memory for synchronously storing sync patterns to be used in post processing to reconstitute trace data of a trace session.
Claim 12
Dependent Claim
56 words
The apparatus as set forth in claim 5, wherein each FPGA further comprises a second on-chip integrated debugging facility for outputting the LE state values as input to at least one trigger; and the apparatus further comprises summing circuitry for generating at least one sum of the LE signal state values for at least one trigger.
Claim 13
Dependent Claim
68 words
The apparatus as set forth in claim 10, wherein the FPGAs are distributively disposed in a plurality of logic boards, the summing circuitry comprises a plurality of at least one partial sum circuit distributively disposed on the logic boards and coupled to the FPGAs on the same logic board for generating a plurality of partial sums of the LE signal state values for the at least one trigger.
Claim 14
Dependent Claim
103 words
In an emulation system, a method for performing fully visible tracing of an emulation, the method comprising the steps of: a) outputting signal state values for all logic elements (LEs) of each field programmable gate array (FPGA) of the emulation system used for emulating a circuit design; b) capturing and storing the LE signal state values output into memory locations of a trace memory in a deterministic locality topology, under which the relative memory location within a block of memory locations used for storing a clock cycle of signal state values where the signal state value of a LE is stored is predeterminable.
Claim 15
Dependent Claim
103 words
In an emulation system, a method for performing fully visible tracing of an emulation, the method comprising the steps of: a) outputting signal state values for all logic elements (LEs) of each field programmable gate array (FPGA) of the emulation system used for emulating a circuit design; b) capturing and storing the LE signal state values output into memory locations of a trace memory in a deterministic locality topology, under which the relative memory location within a block of memory locations used for storing a clock cycle of signal state values where the signal state value of a LE is stored is predeterminable.
Claim 16
Dependent Claim
56 words
The method as set forth in claim 12, wherein the FPGAs are distributively disposed in a plurality of logic boards, and step (b) comprises capturing and storing the LE signal state values output in a plurality of trace memory units correspondingly coupled to the FPGAs and disposed in the same logic board as the coupled FPGA.
Claim 17
Dependent Claim
40 words
The method as set forth in claim 13, wherein step (b) further comprises generating trace memory addresses on each logic board locally and providing the locally generated trace memory addresses to the trace memory units of the corresponding logic boards.
Claim 18
Dependent Claim
45 words
The method as set forth in claim 13, wherein step (b) further comprises storing the signal state value of a LE in the same relative offset location within a block of memory locations used for storing the LE state values output for a clock cycle.
Claim 19
Dependent Claim
26 words
The method as set forth in claim 15, wherein step (b) further comprises storing trace data into the trace memory units in a wrap around manner.
Claim 20
Dependent Claim
66 words
The method as set forth in claim 16, wherein the method further comprises the step of (c) storing a plurality of identical sync patterns in a sync memory for a trace session, one sync pattern per clock cycle, and each sync pattern being stored synchronously at the same time the corresponding signal state values of a particular clock cycle are stored into the trace memory unit.
Claim 21
Dependent Claim
113 words
A computer system comprising means for compiling and mapping a circuit design to logic elements (LE) of an emulation system including means for generating a cross reference file for cross referencing circuit elements of the circuit design to relative memory locations within a block of memory locations of a trace memory used to store a clock cycle of signal state values of the LEs where the signal state values of the LEs onto which the circuit elements are mapped are stored, the emulation system being equipped to capture and store signal state values of all LEs in the trace memory on a clock cycle by clock cycle basis, employing a deterministic locality topology.
Claim 22
Dependent Claim
113 words
A computer system comprising means for compiling and mapping a circuit design to logic elements (LE) of an emulation system including means for generating a cross reference file for cross referencing circuit elements of the circuit design to relative memory locations within a block of memory locations of a trace memory used to store a clock cycle of signal state values of the LEs where the signal state values of the LEs onto which the circuit elements are mapped are stored, the emulation system being equipped to capture and store signal state values of all LEs in the trace memory on a clock cycle by clock cycle basis, employing a deterministic locality topology.
Claim 23
Dependent Claim
70 words
The computer system as set forth in claim 18, wherein the cross reference file comprises a plurality of cross reference records, each cross reference record having identification information of a circuit element, and one or more offset values into each block of memory locations for storing a clock cycle of LE state signal values where the signal state value of the LE onto the circuit element is mapped is stored.
Claim 24
Dependent Claim
117 words
In a computer system, a method for compiling and mapping a circuit design to logic elements (LE) of an emulation system, the method comprising the step of generating a cross reference file for cross referencing circuit elements of the circuit design to relative memory locations within a block of memory locations of a trace memory used to store a clock cycle of signal state values of the LEs where the signal state values of the LEs onto which the circuit elements are mapped are stored, the emulation system being equipped to capture and store signal state values of all LEs in the trace memory on a clock cycle by clock cycle basis, employing a deterministic locality topology.
Claim 25
Dependent Claim
117 words
In a computer system, a method for compiling and mapping a circuit design to logic elements (LE) of an emulation system, the method comprising the step of generating a cross reference file for cross referencing circuit elements of the circuit design to relative memory locations within a block of memory locations of a trace memory used to store a clock cycle of signal state values of the LEs where the signal state values of the LEs onto which the circuit elements are mapped are stored, the emulation system being equipped to capture and store signal state values of all LEs in the trace memory on a clock cycle by clock cycle basis, employing a deterministic locality topology.
Claim 26
Dependent Claim
69 words
The method as set forth in claim 20, wherein the generation step comprises generating a plurality of cross reference records, each cross reference record having identification information of a circuit element, and one or more offset values into each block of memory locations for storing a clock cycle of LE state signal values where the signal state value of the LE onto the circuit element is mapped is stored.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |