Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin

Claim 2

A test system for debugging functional and electrical failures of an integrated circuit, comprising: a programmable debug trigger apparatus disposed internal and integral to said integrated circuit for generating a trigger capture signal a programmed time delay after a plurality of integrated circuit signals satisfy a predetermined relationship to a programmed trigger event; a test access port (TAP) disposed internal and integral to said integrated circuit comprising a TAP latch, said TAP latch coupled to a plurality of test nodes internal to said integrated circuit and responsive to said trigger capture signal for latching a plurality of test node signals present on said plurality of test nodes when said trigger capture signal is received; an external output of said integrated circuit coupled to said TAP and responsive to said trigger capture signal for outputting an external output signal to indicate that said TAP latch has been latched; a reset input of said integrated circuit for resetting said integrated circuit to an initial state; a test access port retrieval system coupled to said TAP; and a diagnostics retrieval system coupled to said integrated circuit and configured to reset said integrated circuit to said initial state, to program said programmed trigger event to a predetermined trigger capture event and said programmed time delay to a first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched.

Claim 3

The test system of claim 1, said diagnostics retrieval system further configured to reset the integrated circuit again, to program said programmed trigger event to said predetermined trigger capture event and said programmed time delay to a second delay value which is incrementally greater than said first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched.

Claim 4

The test system of claim 1, said diagnostics retrieval system comprising: storage means for storing said plurality of test node signals retrieved by said test access port retrieval system.

Claim 5

The test system of claim 1, said diagnostics retrieval system comprising: displaying means for displaying said plurality of test node signals retrieved by said test access port retrieval system.

Claim 6

The test system of claim 1, wherein said test access port retrieval system retrieves said plurality of test node signals from said test access port via a serial line using a JTAG protocol.

Claim 7

The test system of claim 1, wherein said debug trigger apparatus comprises: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a first corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.

Claim 8

The debug trigger apparatus of claim 6, further comprising: a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.

Claim 9

The debug trigger apparatus of claim 7, wherein one or more of the plurality of trigger function blocks is configured to further monitor said iteration counter enable signal and to include said iteration counter enable signal in performing said programmed boolean minterm function.

Claim 12

The method of claim 9, further comprising the step of: (k) storing said retrieved plurality of test node signals retrieved in step (h) in an event trace file.

Claim 13

The method of claim 9, further comprising the step of: (l) displaying said retrieved plurality of test node signals retrieved in step (h) on an event trace screen.

Claim 14

A test system for debugging functional and electrical failures of an integrated circuit, comprising: a programmable debug trigger apparatus disposed internal and integral to said integrated circuit for generating a trigger capture signal a programmed time delay after a plurality of integrated circuit signals satisfy a predetermined relationship to a programmed trigger event; a test access port (TAP) disposed internal and integral to said integrated circuit comprising a TAP latch, said TAP latch coupled to a plurality of test nodes internal to said integrated circuit and responsive to said trigger capture signal for latching a plurality of test node signals present on said plurality of test nodes when said trigger capture signal is received; an external output of said integrated circuit coupled to said TAP and responsive to said trigger capture signal for outputting an external output signal to indicate that said TAP latch has been latched; a reset input of said integrated circuit for resetting said integrated circuit to an initial state; a test access port retrieval system coupled to said TAP; and a diagnostics retrieval system coupled to said integrated circuit and configured to reset said integrated circuit to said initial state, to program said programmed trigger event to a predetermined trigger capture event and said programmed time delay to a first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched, to reset the integrated circuit again, to program said programmed trigger event to said predetermined trigger capture event and said programmed time delay to a second delay value which is incrementally greater than said first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched; wherein said programmable debug trigger apparatus comprises: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a first corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.

Claim 15

A test system for debugging functional and electrical failures of an integrated circuit, comprising: a programmable debug trigger apparatus disposed internal and integral to said integrated circuit for generating a trigger capture signal a programmed time delay after a plurality of integrated circuit signals satisfy a predetermined relationship to a programmed trigger event; a test access port (TAP) disposed internal and integral to said integrated circuit comprising a TAP latch, said TAP latch coupled to a plurality of test nodes internal to said integrated circuit and responsive to said trigger capture signal for latching a plurality of test node signals present on said plurality of test nodes when said trigger capture signal is received; an external output of said integrated circuit coupled to said TAP and responsive to said trigger capture signal for outputting an external output signal to indicate that said TAP latch has been latched; a reset input of said integrated circuit for resetting said integrated circuit to an initial state; a test access port retrieval system coupled to said TAP; and a diagnostics retrieval system coupled to said integrated circuit and configured to reset said integrated circuit to said initial state, to program said programmed trigger event to a predetermined trigger capture event and said programmed time delay to a first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched, to reset the integrated circuit again, to program said programmed trigger event to said predetermined trigger capture event and said programmed time delay to a second delay value which is incrementally greater than said first delay value, to receive said external output signal, and to retrieve said plurality of test node signals from said TAP latch when said external output signal indicates that said TAP latch has been latched; wherein said programmable debug trigger apparatus comprises: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a first corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.

Claim 16

The test system of claim 12, said debug trigger apparatus further comprising: a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.

Claim 17

The test system of claim 13, wherein one or more of the plurality of trigger function blocks of the debug trigger apparatus is configured to further monitor said iteration counter enable signal and to include said iteration counter enable signal in performing said programmed boolean minterm function.