Branch decision encoding scheme

Abstract

Abstract The BRANCH DECISION ENCODING SCHEME shown herein overcomes the limitations of a dedicated debug port on a single chip computer processor. A dedicated debug port resolves many of the problems associated with an add-on logic analyzer, except for its limitation of an eight bit data interface. The 8 bit port is required as a trade-off between the device I/O requirements and development tools. During real time program development, it is virtually impossible to monitor the 24 bit program counter through a port only a third as wide. The present invention solves this problem by taking advantage of the sequential characteristics of application programs. There is a discontinuity in the program counter in only a limited number of situations: branches, jumps, subroutine calls and returns from subroutines, exceptions and returns from exceptions, traps and return from traps, and loopbacks to the tops of loops. Therefore, by monitoring most of these discontinuities, it becomes possible to compress the 24 bit data so that it can be output through the 8 bit port in real time. For example, branch decisions can be defined by noting only that they occurred, and if they were taken or not taken, i.e., "1" or "0". The results of the decision tree are contained within the program and can be reconstructed in an external work station. To maintain synchronization, the absolute value of the program counter is updated periodically as the opportunity presents itself. It is always updated following indirect jumps.

Inventors

• 👤 Dale E. Folwell
• 👤 Ricke W. Clark
• 👤 Donald D. Harenberg

Bibliographic Details