Data processor with real-time diagnostic capability

Claim 2

A data processor with real-time diagnostic capability, comprising: a central processing unit (CPU) coupled to a bus, for continuously executing instructions during a normal operation mode, and for suspending instruction execution in response to a CPU halt signal; a first-in, first-out memory (FIFO) coupled to a portion of said bus, for sequentially storing states of said portion of said bus at corresponding locations of a plurality of locations when a FIFO halt signal is inactive; and a debug controller coupled to said CPU and to said FIFO, for activating both said CPU halt signal and said FIFO halt signal in response to an event condition in a first mode, and for activating said FIFO halt signal but keeping said CPU halt signal inactive in response to said event condition in a second mode, wherein said plurality of locations of said FIFO are observable while said CPU is in said normal operation mode.

Claim 3

The data processor of claim 1, wherein said event condition comprises one of a set consisting of: an activation of an external FIFO halt request, an external breakpoint request, a hardware breakpoint, a software breakpoint, and a trace occurrence.

Claim 4

The data processor of claim 1 further comprising a control register, coupled to said debug controller, for storing a plurality of mode control bits including at least one event modifier bit, said at least one event modifier bit determining whether said debug controller is in said first mode or said second mode.

Claim 5

The data processor of claim I further comprising a serial port coupled to said FIFO and to said debug controller having a serial input for receiving serial input data for selectable storage in either said FIFO or said debug controller, and a serial output for providing serial output data from a selectable one of either said FIFO or said debug controller.

Claim 6

The data processor of claim 1 wherein said CPU has a Harvard architecture (separate program and data spaces) and wherein said portion of said bus comprises a program address bus.

Claim 7

A data processor with real-time diagnostic capability, comprising: a central processing unit (CPU) coupled to a bus, said CPU having a control input for receiving a CPU halt signal, said CPU continuously executing instructions during a normal operation mode, and for suspending instruction execution in response to said CPU halt signal; a serial input/output port having a serial input terminal for receiving serial input data, and an output terminal for transmitting serial data; a first-in, first-out memory (FIFO) coupled to a portion of said bus and to said output terminal of said serial input/output port, for sequentially storing states of said portion of said bus at corresponding locations of a plurality of locations when a FIFO halt signal is inactive; and a debug controller coupled to said output terminal of said serial input/output port, for activating both said CPU halt signal and said FIFO halt signal in response to an event condition in a first mode, and for activating said FIFO halt signal but keeping said CPU halt signal inactive in response to said event condition in a second mode, wherein said plurality of locations of said FIFO are observable while said CPU is in said normal operation mode.

Claim 8

A data processor with real-time diagnostic capability, comprising: a central processing unit (CPU) coupled to a bus, said CPU having a control input for receiving a CPU halt signal, said CPU continuously executing instructions during a normal operation mode, and for suspending instruction execution in response to said CPU halt signal; a serial input/output port having a serial input terminal for receiving serial input data, and an output terminal for transmitting serial data; a first-in, first-out memory (FIFO) coupled to a portion of said bus and to said output terminal of said serial input/output port, for sequentially storing states of said portion of said bus at corresponding locations of a plurality of locations when a FIFO halt signal is inactive; and a debug controller coupled to said output terminal of said serial input/output port, for activating both said CPU halt signal and said FIFO halt signal in response to an event condition in a first mode, and for activating said FIFO halt signal but keeping said CPU halt signal inactive in response to said event condition in a second mode, wherein said plurality of locations of said FIFO are observable while said CPU is in said normal operation mode.

Claim 9

The data processor of claim 6, wherein said event condition comprises one of a set consisting of: an activation of an external FIFO halt signal, an external breakpoint request, a hardware breakpoint, a software breakpoint, and a trace occurrence.

Claim 10

The data processor of claim 7 further comprising a control register, coupled to said debug controller, for storing a plurality of mode control bits including at least one event modifier bit, said at least one event modifier bit determining whether said debug controller is in said first mode or said second mode.

Claim 11

The data processor of claim 6 wherein said CPU has a Harvard architecture (separate program and data spaces) and wherein said portion of said bus comprises a program address bus.

Claim 12

A diagnostic circuit, comprising: a serial input port having a serial input terminal for receiving serial input data, and an output terminal; a first-in, first-out memory (FIFO) coupled to a portion of a bus and to said output terminal of said serial input port, for sequentially storing states of said portion of said bus at corresponding locations of a plurality of locations when a FIFO halt signal is inactive; a debug controller coupled to said output terminal of said serial input/output port, for activating both a CPU halt signal and said FIFO halt signal in response to an event condition in a first mode, and for activating said FIFO halt signal but keeping said CPU halt signal inactive in response to said event condition in a second mode; and a control register, coupled to said debug controller, for storing a plurality of control bits including at least one event modifier bit, said at least one event modifier bit determining whether said debug controller is in said first mode or said second mode, wherein said plurality of locations of said FIFO are observable in said second mode.

Claim 13

A diagnostic circuit, comprising: a serial input port having a serial input terminal for receiving serial input data, and an output terminal; a first-in, first-out memory (FIFO) coupled to a portion of a bus and to said output terminal of said serial input port, for sequentially storing states of said portion of said bus at corresponding locations of a plurality of locations when a FIFO halt signal is inactive; a debug controller coupled to said output terminal of said serial input/output port, for activating both a CPU halt signal and said FIFO halt signal in response to an event condition in a first mode, and for activating said FIFO halt signal but keeping said CPU halt signal inactive in response to said event condition in a second mode; and a control register, coupled to said debug controller, for storing a plurality of control bits including at least one event modifier bit, said at least one event modifier bit determining whether said debug controller is in said first mode or said second mode, wherein said plurality of locations of said FIFO are observable in said second mode.

Claim 14

The data processor of claim 10, wherein said event condition comprises one of a set consisting of: an activation of an external FIFO halt signal, an external breakpoint request, a hardware breakpoint, a software breakpoint, and a trace occurrence.