US4813009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for determining internal status of a processor
Assignee: Tektronix Inc
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Filing: 1984-11-02
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Granted: 1989-03-14
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Expires: 2004-11-02
Abstract
Abstract An improved method and apparatus is disclosed for determining the internal state of a processor without disturbing the operational environment of the processor. A two phase process is employed. In the first phase, external signals produced by the processor in the execution of a known program are monitored and recorded for subsequent analysis. In the second phase, the recorded information is analyzed in the light of the known characteristic of the processor, the program it was executing, and the signals recorded during the first phase. The internal state of the processor is thereby determined after the execution of each instruction. In addition, provisions are made for the specification of breakpoints, and the examination of simulated status of the processor on the occurrence of the breakpoints.
Inventors
- 👤 James L. Tallman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:41
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3466; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
255 words
Apparatus for determining status of a processor during execution of a plurality of instructions comprising a program from infomation descriptive of the processor and externally available address, data and control signals produced by the operation of the processor during the continuous execution of the program, comprising: first storage means coupled to the processor for storing information representative of the externally available address, data and control signals produced by the operation of the processor during the continuous execution of the program; interface means responsive to an operator for receiving information representative of a selected status condition of the processor; simulation means responsive to said first storage means, said interface means, and the information descriptive of the processor for producing information representative of a simulated status of the processor in response to the execution of an instruction; second storage means responsive to the simulation means for storing information representative of the simulated status of the processor; third storage means responsive to said interface means for storing information representative of the selected status condition of the processor; monitoring means responsive to said second and third storage means for detecting the occurrence of information representative of a simulated status of the processor according to information representative of the selected status condition of the processor; processor state display means responsive to said second storage means and the detection by said monitoring means for selecting information representative of the simulated status of the processor or display; and, display means responsive to said processor state display means for displaying the selected information.
Claim 2
Dependent Claim
255 words
Apparatus for determining status of a processor during execution of a plurality of instructions comprising a program from infomation descriptive of the processor and externally available address, data and control signals produced by the operation of the processor during the continuous execution of the program, comprising: first storage means coupled to the processor for storing information representative of the externally available address, data and control signals produced by the operation of the processor during the continuous execution of the program; interface means responsive to an operator for receiving information representative of a selected status condition of the processor; simulation means responsive to said first storage means, said interface means, and the information descriptive of the processor for producing information representative of a simulated status of the processor in response to the execution of an instruction; second storage means responsive to the simulation means for storing information representative of the simulated status of the processor; third storage means responsive to said interface means for storing information representative of the selected status condition of the processor; monitoring means responsive to said second and third storage means for detecting the occurrence of information representative of a simulated status of the processor according to information representative of the selected status condition of the processor; processor state display means responsive to said second storage means and the detection by said monitoring means for selecting information representative of the simulated status of the processor or display; and, display means responsive to said processor state display means for displaying the selected information.
Claim 3
Dependent Claim
34 words
Apparatus as recited in claim 1, wherein said simulation means further comprises means for producing information representative of a simulated status of the processor in response to the execution of a plurality of instructions.
Claim 4
Dependent Claim
33 words
Apparatus as recited in claim 1, wherein said third storage means responsive to said interface means further comprises means for storing information representative of a plurality of selected status conditions of the processor.
Claim 5
Dependent Claim
44 words
Apparatus as recited in claim 3, wherein said monitoring means further comprises means for detecting the occurrence of information representative of a simulated status of the processor according to information representative of any one of the plurality of selected status conditions of the processor.
Claim 6
Dependent Claim
36 words
Apparatus as recited in claim 1, further comprising breakpoint display means responsive to said interface means and to said third storage means for selecting information for display representative of the selected status condition of the processor.
Claim 7
Dependent Claim
39 words
Apparatus as recited in claim 5, wherein said display means further comprises means responsive to the selected information for display by said breakpoint display means for displaying the selected information representative of the selected status condition of the processor.
Claim 8
Dependent Claim
38 words
Apparatus as recited in claim 3, further comprising breakpoint display means responsive to said interface means and to said third storage means for selecting information for display representative of the plurality of selected status condition of the processor.
Claim 9
Dependent Claim
30 words
Apparatus as recited in claim 7, wherein said display means further comprises means responsive to the selected information for display by said breakpoint display means for displaying the selected information.
Claim 10
Dependent Claim
26 words
Apparatus as recited in claim 1 further comprising means for deleting information representative of the selected status condition of the procesor from said third storage means.
Claim 11
Dependent Claim
37 words
Apparatus as recited in claim 3 further comprising means for deleting information representative of a selected status condition from the information representative of the plurality of selected status conditions of the processor from said third storage means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |