Debug circuit of a signal processor

Claim 2

A debug circuit of a signal processor, comprising: a program memory for storing a signal processing program and a debug program; means for decoding said signal processing program and said debug program to provide commands in a signal processing mode and a debug mode, respectively; means for transferring a program running state of an internal circuit of said signal processor to an external circuit, said transferring means receiving a data load signal and a clock signal from said external circuit to control a speed of transferring said program running state; wherein said debug program is decoded in said decoding means to drive said transferring means, providing said debug mode, and to halt said signal processing mode, and said signal processing mode is resumed in response to said data load signal, when said transferring means starts providing said program running state to said external circuit.

Claim 3

A debug circuit of a signal processor, according to claim 1, wherein: said decoding means controls a program counter to halt operation for generating an address signal for said signal processing program, when said debug program is decoded.

Claim 4

A debug circuit of a signal processor, according to claim 1, wherein said transferring means includes: a latch register for latching said state supplied through an internal data bus from said internal circuit, when said debug program is decoded; a shift register for providing said state supplied from said latch register to said external circuit by receiving an externally supplied reading signal; and a flip-flop for providing a first control signal to said decoding means, so that said signal processing mode is halted to start said debug mode, and a second control signal to said decoding means, so that said signal processing mode is restored to be continued by stopping said debug mode.

Claim 5

A debug circuit for a signal processor, comprising: a latch register for latching data to be supplied from said signal processor through an inner bus line thereof to an external circuit in accordance with a data latch signal; a shift register for latching said data in said latch register in accordance with a data load signal from an external circuit and outputting said data; a flip-flop which is set by said data latch signal and is reset by said data load signal; a program counter for generating an address signal; a program memory for storing program data and debug command data, said program memory being responsive to said address signal for reading out program data or debug command data; a command decoder means for decoding said debug command data read from said program memory for generating said data latch signal in response to data debug command; means responsive to an output state of said flip-flop for controlling output of said command decoder means ; whereby a program running state is supplied through said shift register to an external circuit in response to said debug command data, and an ordinary program operation is resumed while said shift register outputs said data latched in said shift register.

Claim 6

A debug circuit for a signal processor, comprising: a latch register for latching data to be supplied from said signal processor through an inner bus line thereof to an external circuit in accordance with a data latch signal; a shift register for latching said data in said latch register in accordance with a data load signal from an external circuit and outputting said data; a flip-flop which is set by said data latch signal and is reset by said data load signal; a program counter for generating an address signal; a program memory for storing program data and debug command data, said program memory being responsive to said address signal for reading out program data or debug command data; a command decoder means for decoding said debug command data read from said program memory for generating said data latch signal in response to data debug command; means responsive to an output state of said flip-flop for controlling output of said command decoder means ; whereby a program running state is supplied through said shift register to an external circuit in response to said debug command data, and an ordinary program operation is resumed while said shift register outputs said data latched in said shift register.

Claim 7

A debug circuit of a signal processor according to claim 4: wherein said program memory includes a first memory for storing said program data and a second memory for storing said debug command data; and wherein said program counter is connected to receive an input from an interrupt control circuit in response to a debug control signal supplied to said interrupt control circuit and wherein said program counter is controlled to operate in one of an ordinary program operation and an debug mode.

Claim 8

A debug circuit of a signal processor, comprising: a memory for storing a series of instructions to be conducted in program operation; means for decoding said instructions read from said memory to generate control signals for conduct of said instructions; a register for latching data supplied in response to a predetermined control signal in said control signals; means for supplying data latched in said register to an exterior in response to an external read instruction signal; a flip-flop for taking a first state in response to said predetermined control signal, and a second state in response to said external read instruction signal; and means for interrupting conduct of said instructions, when said flip-flop is in said first state, and continuing said conduct of said instructions, when said flip-flop is in said second state.

Claim 9

A debug circuit of a signal processor, comprising: a memory for storing a series of instructions to be conducted in program operation; means for decoding said instructions read from said memory to generate control signals for conduct of said instructions; a register for latching data supplied in response to a predetermined control signal in said control signals; means for supplying data latched in said register to an exterior in response to an external read instruction signal; a flip-flop for taking a first state in response to said predetermined control signal, and a second state in response to said external read instruction signal; and means for interrupting conduct of said instructions, when said flip-flop is in said first state, and continuing said conduct of said instructions, when said flip-flop is in said second state.