US5751735A
Expired / Lapsed
US
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Integrated debug trigger method and apparatus for an integrated circuit
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1996-11-14
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Granted: 1998-05-12
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Expires: 2016-11-14
Abstract
Abstract Presented is an internal integrated debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit chip. The debug trigger apparatus includes a plurality of software programmable trigger registers and a plurality of software programmable trigger function blocks. Each trigger register monitors a plurality of integrated circuit signals which may include signals sent to the external pins of the integrated circuit and signals present internal to the chip. If the value of the monitored signals matches the programmed trigger condition, the trigger register produces a trigger match signal. Each trigger function block receives a combination of the trigger match signals generated by the trigger registers and each computes its programmed boolean minterm function on its inputs. Each trigger function block produces a trigger capture signal which may be true or false according to the computed function of the inputs. The debug trigger may also include a programmable iteration counter which allows for repetition of a trigger condition before it is provided external to the chip. The output of the iteration counter may be connected as input to one or more of the other trigger registers to allow for different start and end conditions.
Inventors
- 👤 Paul G. Tobin
- 👤 Hosein Naaseh-Shahry
- 👤 Stephen R. Undy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
170 words
A debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit, comprising: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.
Claim 2
Dependent Claim
170 words
A debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit, comprising: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to receive a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; and a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay.
Claim 3
Dependent Claim
60 words
The debug trigger apparatus of claim 1, wherein said programmed boolean minterm function is computed by performing a bit-wise logical AND of said plurality of said trigger match signals with a programmed bit mask to produce a bit-wise AND result, and then performing a bit-wise logical OR of bits in said bit-wise AND result to produce said trigger capture signal.
Claim 4
Dependent Claim
95 words
The debug trigger apparatus of claim 1, wherein each of said plurality of trigger registers comprise: a sampler latch configured to sample said plurality of said integrated circuit signals according to a system clock signal and hold as output a sampled signal; a pattern latch configured to set a programmable pattern value according to a set pattern program command and hold as output a pattern signal; and a comparator configured to compare said sampled signal and said pattern signal, and to output a trigger match signal when said sampled signal and said pattern signal match.
Claim 5
Dependent Claim
71 words
The debug trigger apparatus of claim 3, wherein each of said plurality of trigger registers further comprise: a mask latch configured to set a programmable mask value according to a set mask program command and hold as output a mask signal; wherein said comparator is configured to ignore, for comparison purposes, bits of said sampled signal and said pattern signal which are masked according to masked bits in said mask signal.
Claim 6
Dependent Claim
75 words
The debug trigger apparatus of claim 1, further comprising: a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.
Claim 7
Dependent Claim
43 words
The debug trigger apparatus of claim 5, wherein one or more of the plurality of trigger function blocks is configured to further monitor said iteration counter enable signal and to include said iteration counter enable signal in performing said programmed boolean minterm function.
Claim 8
Dependent Claim
33 words
The debug trigger apparatus of claim 1, wherein said plurality of programmable trigger registers comprise an instruction address trigger register which is configured to monitor instruction addresses from an internal instruction address bus.
Claim 9
Dependent Claim
30 words
The debug trigger apparatus of claim 1, wherein said plurality of programmable trigger registers comprise a data address trigger register which monitors data addresses from an internal data address bus.
Claim 10
Dependent Claim
30 words
The debug trigger apparatus of claim 1, wherein said plurality of programmable trigger registers comprise an instruction data trigger register which monitors an instruction pattern on an internal instruction bus.
Claim 11
Dependent Claim
242 words
A debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit, comprising: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to said plurality of trigger registers and receiving a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay; and a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.
Claim 12
Dependent Claim
242 words
A debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit, comprising: a plurality of programmable trigger registers disposed internal and integral to said integrated circuit, each trigger register configured to receive a plurality of integrated circuit signals, to compare each of said plurality of integrated circuit signals of said integrated circuit to a programmed trigger condition, and to produce a trigger match signal when said plurality of integrated circuit signals match said programmed trigger condition; a plurality of programmable trigger function blocks disposed internal and integral to said integrated circuit, each trigger function block coupled to said plurality of trigger registers and receiving a plurality of said trigger match signals and performing a programmed boolean minterm function on the monitored trigger match signals to produce a trigger capture signal; a programmable timer disposed internal and integral to said integrated circuit enabled by said trigger capture signal of a corresponding one of said programmable trigger function blocks to generate a timer enable signal upon completion of a programmed time delay; and a programmable iteration counter disposed internal and integral to said integrated circuit and coupled to receive said trigger capture signal of a second corresponding one of said programmable trigger function blocks, said programmable iteration counter generating an iteration count enable signal upon receipt of said trigger capture signal of said second corresponding one of said programmable trigger function blocks a programmed iteration count number of times.
Claim 13
Dependent Claim
51 words
The debug trigger apparatus of claim 10, said plurality of programmable trigger function blocks comprising a first trigger function block, a second trigger function block, and a third trigger function block, wherein each produces respectively a first trigger capture signal, a second trigger capture signal, and a third trigger capture signal.
Claim 14
Dependent Claim
26 words
The debug trigger apparatus of claim 11, wherein said iteration counter is configured to receive the first trigger capture signal from said first trigger function block.
Claim 15
Dependent Claim
35 words
The debug trigger apparatus of claim 12, wherein said first and second trigger function blocks are further configured to monitor and use said iteration count enable signal to perform their respective programmed boolean minterm functions.
Claim 16
Dependent Claim
26 words
The debug trigger apparatus of claim 13, wherein said programmable timer is configured to receive said second trigger capture signal from said second trigger function block.
Claim 17
Dependent Claim
84 words
The debug trigger apparatus of claim 13, wherein said plurality of trigger registers comprise an instruction address trigger register which monitors instruction addresses from an internal instruction address bus and produces an instruction address trigger match signal, a data address trigger register which monitors data addresses from an internal data address bus and produces a data address trigger match signal, and an instruction data trigger register which monitors an instruction pattern on an internal instruction bus and produces an instruction data trigger match signal.
Claim 18
Dependent Claim
95 words
The debug trigger apparatus of claim 10, wherein each of said plurality of programmable trigger registers comprise: a sampler latch configured to sample said plurality of integrated circuit signals according to a system clock signal and hold as output a sampled signal; a pattern latch configured to set a programmable pattern value according to a set pattern program command and hold as output a pattern signal; and a comparator configured to compare said sampled signal and said pattern signal, and to output a trigger match signal when said sampled signal and said pattern signal match.
Claim 19
Dependent Claim
71 words
The debug trigger apparatus of claim 16, wherein each of said plurality of trigger registers further comprise: a mask latch configured to set a programmable mask value according to a set mask program command and hold as output a mask signal; wherein said comparator is configured to ignore, for comparison purposes, bits of said sampled signal and said pattern signal which are masked according to masked bits in said mask signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |