US5951696A
Expired / Lapsed
US
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Debug system with hardware breakpoint trap
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-11-14
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Granted: 1999-09-14
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Expires: 2016-11-14
Abstract
Abstract Disclosed herein is sophisticated but low-cost debug hardware which may be used to identify the root cause of a functional or electrical problem in a microprocessor chip. The debug hardware provides for generating a hardware breakpoint trap (HBT) in response to programmed combinations of internal signal triggers, and if desired, a HBT may be delayed through one or more occurrences of a programmed trigger combination via use of an iteration counter. Apparatus for generating and handling a HBT may comprise one or more trigger means, one or more event generation means, and debug software comprising code for 1) preserving the current architected state of a microprocessor upon generation of a HBT, 2) vectoring to and initiating execution of trap handler code, and 3) restoring said preserved current architected state after said trap handler code has been executed. Each of the trigger means is implemented internally to the microprocessor so as to monitor signals of the microprocessor and generate a trigger as programmed values of the signals are detected. Each of the event generation means is also implemented internally to the microprocessor, and may be used to generate a HBT in response to a programmed combination of the number of triggers generated by said trigger means. The debug software is stored in one or more memories accessible to, but possibly external to, the microprocessor.
Inventors
- 👤 Hosein Naaseh
- 👤 Paul G. Tobin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
171 words
Apparatus for generating and handling a hardware breakpoint trap (HBT) internally to a microprocessor, comprising: a) a plurality of trigger means, internal to the microprocessor, for monitoring signals of the microprocessor and generating a number of triggers as programmed values of the signals are detected, wherein each of the plurality of trigger means is associated with, and monitors signals on, a different address bus or data bus of the microprocessor; b) one or more event generation means, internal to the microprocessor, for generating a HBT in response to a programmed combination of the number of triggers generated by said plurality of trigger means; and c) debug software stored in one or more memories accessible to the microprocessor, comprising: i) code for preserving a current architected state of the microprocessor upon generation of said HBT; ii) code for vectoring to and initiating execution of trap handler code after said current architected state is preserved; and iii) code for restoring said preserved current architected state after said trap handler code has been executed.
Claim 2
Dependent Claim
171 words
Apparatus for generating and handling a hardware breakpoint trap (HBT) internally to a microprocessor, comprising: a) a plurality of trigger means, internal to the microprocessor, for monitoring signals of the microprocessor and generating a number of triggers as programmed values of the signals are detected, wherein each of the plurality of trigger means is associated with, and monitors signals on, a different address bus or data bus of the microprocessor; b) one or more event generation means, internal to the microprocessor, for generating a HBT in response to a programmed combination of the number of triggers generated by said plurality of trigger means; and c) debug software stored in one or more memories accessible to the microprocessor, comprising: i) code for preserving a current architected state of the microprocessor upon generation of said HBT; ii) code for vectoring to and initiating execution of trap handler code after said current architected state is preserved; and iii) code for restoring said preserved current architected state after said trap handler code has been executed.
Claim 3
Dependent Claim
65 words
Apparatus as in claim 1, wherein each of the one or more trigger means comprises: a) one or more comparison blocks, each comparison block comprising: i) a bitwise sample latch; ii) a bitwise pattern latch; and iii) a comparator receiving an output from the bitwise sample and pattern latches; and b) an output derived from one or more of the one or more comparison blocks.
Claim 4
Dependent Claim
41 words
Apparatus as in claim 2, wherein each of the comparison blocks of the one or more trigger means further comprises a bitwise mask latch, wherein the comparator of a comparison block also receives an output from its corresponding bitwise mask latch.
Claim 5
Dependent Claim
19 words
Apparatus as in claim 1, further comprising a dedicated HBT diagnose register set, accessible only to the debug software.
Claim 6
Independent Claim
116 words
A method of generating and handling a hardware breakpoint trap (HBT) internally to a microprocessor, comprising: a) monitoring signals internal to the microprocessor, said internal signals being carried on a plurality of buses, said plurality of buses comprising data and/or address buses; b) generating a number of triggers as programmed values of the internal signals are detected within the microprocessor; c) generating a HBT in response to a programmed combination of the number of triggers generated; d) preserving a current architected state of the microprocessor upon generation of said HBT; e) vectoring to and executing trap handler code after said current architected state is preserved; and f) restoring the preserved current architected state of the microprocessor.
Claim 7
Independent Claim
116 words
A method of generating and handling a hardware breakpoint trap (HBT) internally to a microprocessor, comprising: a) monitoring signals internal to the microprocessor, said internal signals being carried on a plurality of buses, said plurality of buses comprising data and/or address buses; b) generating a number of triggers as programmed values of the internal signals are detected within the microprocessor; c) generating a HBT in response to a programmed combination of the number of triggers generated; d) preserving a current architected state of the microprocessor upon generation of said HBT; e) vectoring to and executing trap handler code after said current architected state is preserved; and f) restoring the preserved current architected state of the microprocessor.
Claim 8
Dependent Claim
61 words
A method as in claim 5, wherein: a) the method further comprises setting an HBT indicator bit upon generation of said HBT; and b) vectoring to and executing trap handler code comprises: i) first, branching to a high priority machine check address; ii) second, determining that a HBT exists; and iii) third, vectoring to and initiating execution of HBT handler code.
Claim 9
Dependent Claim
28 words
A method as in claim 5, wherein generating said HBT is dependent upon an iteration counter elapsing, wherein the iteration counter is responsive to the number of triggers.
Claim 10
Dependent Claim
38 words
A method as in claim 7, wherein restoring the preserved current architected state of the microprocessor comprises programming the iteration counter so that it expires after detecting two matches of a programmed combination of the number of triggers.
Claim 11
Dependent Claim
52 words
A method as in claim 5, wherein preserving a current architected state of the microprocessor comprises: a) freezing one or more interrupt instruction address queues (IIAQs); b) preserving all shadow registers in their current state; and c) saving one or more architected registers, other than shadow registers, to dedicated HBT diagnose registers.
Claim 12
Dependent Claim
52 words
A method as in claim 9, wherein saving one or more architected registers to dedicated HBT diagnose registers comprises: a) saving an architected interrupt processor status word (IPSW) to a first dedicated HBT diagnose register; and b) saving the one or more IIAQs to one or more additional dedicated HBT diagnose registers.
Claim 13
Dependent Claim
28 words
A method as in claim 10, wherein preserving the current architected state of the microprocessor further comprises saving an architected processor status word (PSW) to the architected IPSW.
Claim 14
Dependent Claim
57 words
A method as in claim 11, wherein restoring the preserved current architected state of the microprocessor comprises: a) restoring the PSW from the IPSW; b) restoring the IPSW from the first dedicated HBT diagnose register; c) restoring the one or more IIAQs from the one or more additional dedicated HBT diagnose registers; and d) unfreezing the IIAQs.
Claim 15
Dependent Claim
52 words
A method as in claim 10, wherein saving one or more IIAQs to one or more additional dedicated HBT diagnose registers comprises saving one or more interrupt instruction address space queues (IIASQs) and one or more interrupt instruction address offset queues (IIAOQs) to the one or more additional dedicated HBT diagnose registers.
Claim 16
Dependent Claim
28 words
A method as in claim 13, wherein preserving the current architected state of the microprocessor further comprises saving an architected processor status word (PSW) to the architected IPSW.
Claim 17
Dependent Claim
58 words
A method as in claim 14, wherein restoring the preserved current architected state of the microprocessor comprises: a) restoring the PSW from the IPSW; b) restoring the IPSW from the first dedicated HBT diagnose register; c) restoring the IIASQs and IIAOQs from the one or more additional dedicated HBT diagnose registers; and d) unfreezing the IIASQs and IIAOQs.
Claim 18
Dependent Claim
31 words
A method as in claim 15, wherein restoring the preserved current architected state of the microprocessor comprises executing a special form HBT return from interrupt instruction from within trap handler code.
Claim 19
Dependent Claim
45 words
A method as in claim 9, wherein vectoring to and executing trap handler code comprises: a) first, branching to a high priority machine check (HPMC) address; b) second, determining that a HBT exists; and c) third, vectoring to and initiating execution of HBT handler code.
Claim 20
Dependent Claim
102 words
A method as in claim 17, wherein determining whether a HBT exists comprises: a) moving contents of a particular general purpose register to a dedicated HBT scratch register; b) moving contents of a HBT control register comprising a bit indicative of whether a HBT exists into the particular general purpose register; and c) if the bit of the particular general purpose register which is indicative of whether a HBT exists is not set, restoring the contents of the particular general purpose register from the contents of the dedicated HBT scratch register and executing HPMC handler code in lieu of HBT handler code.
Claim 21
Dependent Claim
35 words
A method as in claim 18, wherein vectoring to and initiating execution of HBT handler code comprises restoring the contents of the particular general purpose register from the contents of the dedicated HBT scratch register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |