Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes

Claim 2

A data processing system comprising: a central processing unit (CPU) having a first pipelined execution unit and a second pipelined execution unit, each pipelined execution unit selectively having both (1) a normal mode of operation wherein a user programming model and user address space are accessed, via bus circuitry, to perform a predetermined function and (2) a debug mode of operation wherein a debug address space different from the user address space is accessed, via the bus circuitry used for the normal mode of operation, to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined rate and the debug mode of operation executing instructions fetched from the debug address space at a rate substantially equal to the predetermined rate wherein the CPU debugs the data processing system when operating in the debug mode of operation.

Claim 3

The data processing system of claim 1 wherein the data processing system has an operational state before entering the debug mode of operation wherein the debug mode of operation allows the execution of instructions in a non-destructive manner wherein the operational state of the processing system is maintained throughout the debug mode of operation.

Claim 4

The data processing system of claim 1 wherein the data processing system has an operational state which is stored in memory before entering the debug mode of operation wherein the debug mode of operation allows the execution of instructions in a non-destructive manner wherein the operational state of the processing system is restored in the data processing system after the debug mode of operation is exited.

Claim 5

The data processing system of claim 1 wherein the debug mode of operation utilizes data and address bus resources available to the data processing system when in the normal mode of operation wherein the data and address bus resources are used in a substantially similar manner regardless of whether the normal mode of operation or the debug mode of operation is functioning.

Claim 6

The data processing system of claim 1 wherein the debug mode of operation utilizes pipeline, bus interface, and cache resources available to the data processing system when in the normal mode of operation.

Claim 7

The data processing system of claim 1 wherein the debug mode of operation is allowed to selectively access the user address space in addition to the debug address space.

Claim 8

The data processing system of claim 1 wherein the debug mode of operation is allowed to selectively access at least one memory location within the user programming model in addition to being able to access the debug address space.

Claim 9

The data processing system of claim 1 wherein the data processing system has a plurality of output terminals for providing a plurality of control bits, the plurality of control bits being used to indicate what type of external bus access is to be performed external to the data processing system and which address space is to be accessed.

Claim 10

The data processing system of claim 1 wherein the data processing system comprises a logical to physical address translation cache and disables the logical to physical address translation cache when in the debug mode of operation.

Claim 11

The data processing system of claim 1 wherein the data processing system comprises at least one internal cache location for storing one or more of operands and data, the at least one internal cache location being disabled or invalidated when in the debug mode of operation.

Claim 12

The data processing system of claim 1 wherein the data processing system enters the debug mode of operation in response to an interrupt within the data processing system.

Claim 13

The data processing system of claim 11 wherein the interrupt is generated by a reset of the CPU.

Claim 14

The data processing system of claim 11 wherein the interrupt is generated by a plurality of control bits serially shifted into the data processing system and communicated to the CPU.

Claim 15

The data processing system of claim 11 wherein the interrupt is generated in response to both a breakpoint instruction executed within the CPU and an asserted control bit.

Claim 16

The data processing system of claim 11 wherein the interrupt is generated in response to both an asserted trace control bit and an asserted program control register bit.

Claim 17

The data processing system of claim 1 wherein the debug mode of operation is allowed to both write and read information from both the user address space and at least one register within the user programming model.

Claim 18

The data processing system of claim 1 wherein the data processing system can selectively disable, when the data processing system is operating in the debug mode of operation, one circuit selected for a group consisting of: a floating point unit within the data processing system, a branch cache within the data processing system, a write buffer within the data processing system, a superscalar dispatch circuit within the data processing system, an address translation cache (ATC) within the data processing system, an instruction cache within the data processing system, and a data cache within the data processing system.

Claim 19

The data processing system of claim 1 wherein the data processing system has a terminal for receiving one or more serially-communicated instructions to be communicated to the CPU during the debug mode of operation.

Claim 20

The data processing systems of claim 18 wherein the one or more serially-communicated instructions is at least one instruction selected from a group consisting of: an instruction which is used to invalidate a cache internal to the data processing system, an instruction which is used to flush at least one cache internal to the data processing system, and an instruction which is used to perform a cache push operation for at least one cache within the data processing system.

Claim 21

The data processor of claim 1 wherein the CPU is a pipelined CPU.

Claim 22

The data processor of claim 20 wherein the CPU has a control bit which, when asserted, allows the CPU to run in a non-pipelined mode of operation.

Claim 23

The data processor of claim 21 wherein the CPU is a superscaler architecture having more than one pipeline unit operating in parallel and has a single instruction step mode of debugging wherein one instruction is executed at a single point in time.

Claim 24

The data processing system of claim 1 wherein the data processing system can be programmed to tri-state a plurality of output terminals and ignore a plurality of input terminals when in the debug mode of operation.

Claim 25

The data processing system of claim 23 wherein a debug controller external to the data processing system may be used to perform bus operations when the plurality of output terminals is tri-stated.

Claim 26

The data processing system of claim 1 wherein the data processor is capable of entering a halt mode of operation.

Claim 27

A data processor comprising: a plurality of terminals for communicating control information, data bits, and address bits external to the data processor and receiving control information and data bits from external to the data processor; a bus interface unit coupled to the plurality of terminals; a data cache coupled to the bus interface unit for storing data received via the plurality of terminals; an instruction cache coupled to the bus interface unit for storing instructions received via the plurality of terminals; an instruction prefetch unit for receiving instructions from the instruction cache and providing control signal outputs; and a first pipelined execution unit and a second pipelined execution unit for receiving data from the data cache and receiving the control signal outputs from the instruction prefetch unit and executing a plurality of instructions using data from the data cache, each pipelined execution unit selectively having both a normal mode of operation wherein a user programming model and user address space are accessed to perform a predetermined function and a debug mode of operation wherein a debug address space different from the user address space is accessed to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined frequency, the instructions being provided via the plurality of terminals, the debug mode of operation executing instructions fetched from the debug address space at a frequency substantially equal to the predetermined frequency.

Claim 28

A data processor comprising: a plurality of terminals for communicating control information, data bits, and address bits external to the data processor and receiving control information and data bits from external to the data processor; a bus interface unit coupled to the plurality of terminals; a data cache coupled to the bus interface unit for storing data received via the plurality of terminals; an instruction cache coupled to the bus interface unit for storing instructions received via the plurality of terminals; an instruction prefetch unit for receiving instructions from the instruction cache and providing control signal outputs; and a first pipelined execution unit and a second pipelined execution unit for receiving data from the data cache and receiving the control signal outputs from the instruction prefetch unit and executing a plurality of instructions using data from the data cache, each pipelined execution unit selectively having both a normal mode of operation wherein a user programming model and user address space are accessed to perform a predetermined function and a debug mode of operation wherein a debug address space different from the user address space is accessed to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined frequency, the instructions being provided via the plurality of terminals, the debug mode of operation executing instructions fetched from the debug address space at a frequency substantially equal to the predetermined frequency.

Claim 29

The data processor of claim 26 further comprising: external memory coupled to the plurality of terminals, the external memory having a portion which is defined as user address space for use in the normal mode of operation and default address space different from the user address space for use during the debug mode of operation.

Claim 30

The data processor of claim 26 wherein the pipelined execution unit has a first pipeline unit and a second pipeline unit wherein both pipeline units execute processor instructions.

Claim 31

A data processor comprising: a plurality of terminals used for receiving data and instructions from external to the data processor, the data and instructions being normal data and instructions if read from a first address space external to the data processor and being debug data and instructions if read from a debug address space; a central processing unit (CPU) within the data processor and coupled to the plurality of terminals, the CPU having a first pipelined execution unit and a second pipelined execution unit, each pipelined execution unit selectively having both a normal mode of operation wherein a user programming model and the first address space are accessed to perform a predetermined function and a debug mode of operation wherein the debug address space accessed during the debug mode of operation is different from the user address space and is accessed to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined rate and the debug mode of operation executing instructions fetched from the debug address space at a rate substantially equal to the predetermined rate, the debug mode of operation operating in a non-destructive manner wherein the instructions and state associated with the user address space is not adversely altered via the debug mode of operation.

Claim 32

A data processor comprising: a plurality of terminals used for receiving data and instructions from external to the data processor, the data and instructions being normal data and instructions if read from a first address space external to the data processor and being debug data and instructions if read from a debug address space; a central processing unit (CPU) within the data processor and coupled to the plurality of terminals, the CPU having a first pipelined execution unit and a second pipelined execution unit, each pipelined execution unit selectively having both a normal mode of operation wherein a user programming model and the first address space are accessed to perform a predetermined function and a debug mode of operation wherein the debug address space accessed during the debug mode of operation is different from the user address space and is accessed to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined rate and the debug mode of operation executing instructions fetched from the debug address space at a rate substantially equal to the predetermined rate, the debug mode of operation operating in a non-destructive manner wherein the instructions and state associated with the user address space is not adversely altered via the debug mode of operation.

Claim 33

The data processor of claim 29 wherein the non-destructive manner of operation is further accomplished by storing a user programmers model associated with the user address space to memory when debug mode of operation is entered and restoring the user programmers model from memory to the data processor when the debug mode of operation is terminated.

Claim 34

An integrated circuit data processor comprising: a first pipeline execution unit having a normal mode of operation for executing normal instructions at an execution speed and having a normal mode state while executing, a debug mode of operation which is selectively set to execute the normal instructions at a speed substantially equal to the execution speed to test the integrated circuit data processor for proper functioning while the normal mode state is preserved, and a plurality of execution stages; a second pipeline execution unit having a normal mode of operation and a debug mode of operation, and a plurality of execution stages; and circuitry which allows the first pipeline execution unit to selectively execute instructions in a non-pipelined manner wherein only one instruction at a time is allowed to be transferred through more than one execution stage in the plurality of the execution stages of the first pipeline execution unit.

Claim 35

An integrated circuit data processor comprising: a first pipeline execution unit having a normal mode of operation for executing normal instructions at an execution speed and having a normal mode state while executing, a debug mode of operation which is selectively set to execute the normal instructions at a speed substantially equal to the execution speed to test the integrated circuit data processor for proper functioning while the normal mode state is preserved, and a plurality of execution stages; a second pipeline execution unit having a normal mode of operation and a debug mode of operation, and a plurality of execution stages; and circuitry which allows the first pipeline execution unit to selectively execute instructions in a non-pipelined manner wherein only one instruction at a time is allowed to be transferred through more than one execution stage in the plurality of the execution stages of the first pipeline execution unit.

Claim 36

The integrated circuit data processor of claim 31 wherein the second pipeline execution unit has circuitry which allows the second pipelined execution unit to selectively execute instructions in a non-pipelined manner.

Claim 37

The integrated circuit data processor of claim 31 wherein the first pipeline execution unit is executing instructions in a pipelined manner and the second pipeline execution unit is operating in an idle state wherein no instructions are being executed.

Claim 38

The integrated circuit data processor of claim 31 wherein the first pipeline execution unit is executing instructions in a single-step non-pipelined manner and the second pipeline execution unit is in an idle state wherein no instructions are being executed.

Claim 39

The integrated circuit data processor of claim 31 wherein the first pipeline execution unit is executing instructions in a single-step non-pipelined manner and the second integrated circuit is executing instructions in a pipelined manner.

Claim 40

The integrated circuit data processor of claim 31 wherein the first pipeline execution unit may be operated in a single step debug mode wherein only one instruction is executed by the first pipeline execution unit at a time and the debug mode of operation is entered after the execution of every instruction.

Claim 41

An integrated circuit data processor comprising: a first pipeline execution unit having a normal mode of operation and a debug mode of operation; a second pipeline execution unit having a normal mode of operation and a debug mode of operation, the second pipelined execution unit having both the normal mode of operation wherein a user programming model and user address space are accessed to perform a predetermined function and the debug mode of operation wherein a debug address space different from the user address space is accessed to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined rate and the debug mode of operation executing instructions fetched from the debug address space at a rate substantially equal to the predetermined rate; and circuitry for selectively tri-stating at least one output terminal of the data processor so that an external debug circuit can perform bus operations when the integrated circuit data processor is operating in the debug mode of operation.

Claim 42

An integrated circuit data processor comprising: a first pipeline execution unit having a normal mode of operation and a debug mode of operation; a second pipeline execution unit having a normal mode of operation and a debug mode of operation, the second pipelined execution unit having both the normal mode of operation wherein a user programming model and user address space are accessed to perform a predetermined function and the debug mode of operation wherein a debug address space different from the user address space is accessed to perform another predetermined function, the normal mode of operation executing instructions fetched from the user address space at a predetermined rate and the debug mode of operation executing instructions fetched from the debug address space at a rate substantially equal to the predetermined rate; and circuitry for selectively tri-stating at least one output terminal of the data processor so that an external debug circuit can perform bus operations when the integrated circuit data processor is operating in the debug mode of operation.

Claim 43

The data processing system of claim 1 wherein the normal mode of operation executes instructions from a normal mode instruction set and wherein the debug mode of operation executes the instructions from the normal mode instructions set.

Claim 46

The method of claim 39 wherein the step of placing the first pipeline unit into a debug mode of operation comprises: reading debug and user instructions are read using the same bus controller and same address/data busses where debug instruction run at the predetermined pipeline speed.

Claim 47

The method of claim 39 wherein the step of placing the first pipeline unit into a debug mode of operation comprises: reading debug and user instructions are read using the same bus controller and same address/data busses where debug instruction run at a speed lower than the predetermined pipeline speed due to non-pipelined debug execution in the first pipeline unit.

Claim 48

The method of claim 39 wherein the step of placing the first pipeline unit into a debug mode of operation comprises: reading debug and user instructions wherein the debug and user instructions are both selected from a substantially similar instruction set so that the debug mode of operation was a same level of functionality as the normal mode of operation.