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US5812414A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for performing simulation using a hardware logic emulation system

Assignee: Quickturn Design Systems Inc
•
Filing: 1996-12-19
•
Granted: 1998-09-22
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Expires: 2016-12-19
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Abstract

Abstract A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Inventors

  • 👤 Michael R. Butts
  • 👤 Jon A. Batcheller

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 12:30
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/34; G06F30/347; G06F30/39

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 128 words
A method for stimulating a functional circuit with logical stimulus to determine what response is produced by the functional circuit from that input, the method comprising the steps: (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices interconnected by reprogrammable interconnect devices, said functional circuit being implemented by at least two of said N reprogrammable logic devices; (b) converting the logical stimulus into input electrical signals; (c) inputting said electrical signals to said N reconfigurable logic apparatus which is configured with the functional circuit; (d) receiving output electrical signals from said reconfigurable logic apparatus; and (e) converting said output electrical signals into software form.
Claim 2
Independent Claim 128 words
A method for stimulating a functional circuit with logical stimulus to determine what response is produced by the functional circuit from that input, the method comprising the steps: (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices interconnected by reprogrammable interconnect devices, said functional circuit being implemented by at least two of said N reprogrammable logic devices; (b) converting the logical stimulus into input electrical signals; (c) inputting said electrical signals to said N reconfigurable logic apparatus which is configured with the functional circuit; (d) receiving output electrical signals from said reconfigurable logic apparatus; and (e) converting said output electrical signals into software form.
Claim 3
Dependent Claim 18 words
The method of claim 1 wherein each step is performed in seriatim from step (a) to step (e).
Claim 4
Dependent Claim 19 words
The method of claim 1 wherein each of said N reprogrammable logic devices comprises a field programmable gate array.
Claim 5
Dependent Claim 18 words
The method of claim 1 wherein said software form is translatable by a computer into a user-readable format.
Claim 6
Independent Claim 122 words
A method of simulating a functional circuit design, the method comprising the steps of: (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices interconnected by reprogrammable interconnect devices, said functional circuit being implemented by at least two of said N reprogrammable logic devices; (b) providing a set of stimulus to said reconfigurable logic apparatus having the functional circuit configured therein; (c) collecting a set of responses to said set of stimulus from said reconfigurable logic apparatus having the functional circuit configured therein; and (d) converting said set of responses from a machine readable form to a user-readable form.
Claim 7
Independent Claim 122 words
A method of simulating a functional circuit design, the method comprising the steps of: (a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices interconnected by reprogrammable interconnect devices, said functional circuit being implemented by at least two of said N reprogrammable logic devices; (b) providing a set of stimulus to said reconfigurable logic apparatus having the functional circuit configured therein; (c) collecting a set of responses to said set of stimulus from said reconfigurable logic apparatus having the functional circuit configured therein; and (d) converting said set of responses from a machine readable form to a user-readable form.
Claim 8
Dependent Claim 56 words
The method of claim 5 wherein said providing step comprises the steps of: (a) converting said set of stimulus from a netlist format into a set of input vectors, said input vectors comprising binary data capable of loading into said N reprogrammable logic devices; and (b) loading said binary data into said N reprogrammable logic devices.
Claim 9
Dependent Claim 18 words
The method of claim 5 wherein each step is performed in seriatim from step (a) to step (d).
Claim 10
Dependent Claim 19 words
The method of claim 5 wherein each of said N reprogrammable logic devices comprises a field programmable gate array.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-09-21 2002-03-23 2002-09-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-09-21 2006-03-23 2006-09-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-09-21 2010-03-23 2010-09-22 $7700.00 Window Closed / Lapsed

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