US5537580A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit fabrication using state machine extraction from behavioral hardware description language
Assignee: NXP BV
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Filing: 1994-12-21
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Granted: 1996-07-16
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Expires: 2014-12-21
Abstract
Abstract A method for fabricating an integrated circuit includes the steps of: (a) describing the functionality of an integrated circuit in terms of a behavioral hardware description language, where the hardware description language describes behavior which can be extracted as a state machine; (b) extracting a register level state machine transition table of the state machine from the hardware description language; (c) generating a logic level state transition table representing the state machine from the register level state machine description; (d) creating a state machine structural netlist representing the state machine from the logic level state transition table; and (e) combining the state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist including the state machine to provide a basis for chip compilation, mask layout and integrated circuit fabrication. The method results in a synchronous state machine being extracted from an register-transfer (RT) level representation taken from a scheduled behavioral hardware description language description such as a Verilog or VHDL. Behavioral hardware description language constructs such as "if", "case", "for" statements and sub-program calls can describe the state machine. A logic level state transition table represents each extracted state machine, and each extracted state machine includes control logic produced by previous synthesis phases such as data-path and memory synthesis.
Inventors
- 👤 Jean-Charles Giomi
- 👤 Gerard Tarroux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:22
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
146 words
A method for fabricating an integrated circuit comprising the steps of: describing a functionality of an integrated circuit in terms of a behavioral hardware description language, said hardware description language describing behavior which can be extracted as a state machine; parsing and symbolically simulating said hardware description language to create an intermediate register level representation of said hardware description language; extracting a register level state machine transition table from said intermediate register level representation; generating a logic level state transition table representing said state machine from said register level state machine description; creating a state machine structural netlist representing said state machine from said logic level state transition table; and combining said state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist including said state machine to provide a basis for chip compilation, mask layout and integrated circuit fabrication.
Claim 2
Independent Claim
146 words
A method for fabricating an integrated circuit comprising the steps of: describing a functionality of an integrated circuit in terms of a behavioral hardware description language, said hardware description language describing behavior which can be extracted as a state machine; parsing and symbolically simulating said hardware description language to create an intermediate register level representation of said hardware description language; extracting a register level state machine transition table from said intermediate register level representation; generating a logic level state transition table representing said state machine from said register level state machine description; creating a state machine structural netlist representing said state machine from said logic level state transition table; and combining said state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist including said state machine to provide a basis for chip compilation, mask layout and integrated circuit fabrication.
Claim 3
Dependent Claim
22 words
A method as recited in claim 1 wherein said hardware description language is selected from the group consisting of VHDL and Verilog.
Claim 4
Dependent Claim
57 words
A method as recited in claim 1 wherein said step of parsing and symbolically simulating comprises the steps of: parsing to create a control flow graph including data elements of said integrated circuit; symbolically simulating said control flow graph to create expressions represented by directed-acyclic graphs describing behavior of each data element in said control flow graph.
Claim 5
Dependent Claim
42 words
A method as recited in claim 3 wherein: said step of extracting a register level state machine further includes recognizing a state register synthesis directive and a state encoding; and creating a state register in response to said state register synthesis directive.
Claim 6
Dependent Claim
20 words
A method as recited in claim 4 wherein said state register synthesis directive is provided within said hardware description language.
Claim 7
Dependent Claim
25 words
A method as recited in claim 4 wherein said state register synthesis directive is provided externally to said hardware description language via a user interface.
Claim 8
Dependent Claim
33 words
A method as recited in claim 4 wherein: said register level state transition table is generated incrementally with values and conditions which are extracted from an directed-acyclic graph corresponding to said state register.
Claim 9
Dependent Claim
29 words
A method as recited in claim 7 wherein initial state values are extracted from said directed-acyclic graph corresponding to said state register by a generic state value extraction algorithm.
Claim 10
Dependent Claim
27 words
A method as recited in claim 8 further comprising the step of: processing said directed-acyclic graph using register transfer level nodes to extract said values and conditions.
Claim 11
Dependent Claim
23 words
A method as recited in claim 9 wherein said register transfer level nodes include value nodes, net nodes, if-then-else nodes, and case nodes.
Claim 12
Dependent Claim
54 words
A method as recited in claim 1 further comprising the steps of: partitioning intermediate register level representation into at least one control unit and at least one non-control unit; extracting extraneous control logic from said non-control unit; producing said register level state machine transition table using said control unit and said extraneous control logic.
Claim 13
Dependent Claim
24 words
A method as recited in claim 11 wherein said non-control unit comprises at least one of a memory, a data path, and random logic.
Claim 14
Dependent Claim
45 words
A method as recited in claim 1 further comprising the steps of: creating a state register; creating an directed-acyclic graph corresponding to said state register; and producing a plurality of state values and conditions from said directed-acyclic graph with a generic state value extraction algorithm.
Claim 15
Dependent Claim
60 words
A method as recited in claim 13 wherein extracting said register level state transition table includes using said generic state value extraction algorithm for explicit state value extraction from said directed-acyclic graph, and using said generic state value extraction algorithm for implicit state value extraction from said directed-acyclic graph evaluated when said state register is substituted by a state value.
Claim 16
Independent Claim
157 words
A method of integrated circuit fabrication including register level state machine extraction from a behavioral hardware description language comprising the steps of: inputting a hardware description language into a digital computer with a user input device, said hardware description language describing a state machine in terms of behavior; parsing and symbolically simulating said hardware description language to create an intermediate register level representation of said hardware description language: extracting a register level state machine transition table from said intermediate register level representation with a state machine extraction tool implemented on said computer; generating a logic level state transition table with a logic level state transition table tool implemented on said computer; synthesizing a state machine structural netlist from said logic level state transition table with a state machine compiler tool implemented on said computer; and combining on said computer said state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist.
Claim 17
Independent Claim
157 words
A method of integrated circuit fabrication including register level state machine extraction from a behavioral hardware description language comprising the steps of: inputting a hardware description language into a digital computer with a user input device, said hardware description language describing a state machine in terms of behavior; parsing and symbolically simulating said hardware description language to create an intermediate register level representation of said hardware description language: extracting a register level state machine transition table from said intermediate register level representation with a state machine extraction tool implemented on said computer; generating a logic level state transition table with a logic level state transition table tool implemented on said computer; synthesizing a state machine structural netlist from said logic level state transition table with a state machine compiler tool implemented on said computer; and combining on said computer said state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist.
Claim 18
Dependent Claim
57 words
A method as recited in claim 15 wherein said step of parsing and symbolically simulating comprises the steps of: parsing to create a control flow graph including data elements of said integrated circuit; symbolically simulating said control flow graph to create expressions represented by directed-acyclic graphs describing behavior of each data element in said control flow graph.
Claim 19
Dependent Claim
54 words
A method as recited in claim 16 further comprising the steps of: partitioning intermediate register level representation into at least one control unit and at least one non-control unit; extracting extraneous control logic from said non-control unit; producing said register level state machine transition table using said control unit and said extraneous control logic.
Claim 20
Dependent Claim
40 words
A method as recited in claim 15 wherein said inputting step includes: detecting a state machine synthesis directive; creating a state register in response to said state machine synthesis directive; and creating an directed-acyclic graph corresponding to said state register.
Claim 21
Dependent Claim
28 words
A method as recited in claim 18 wherein said register level state transition table is generated incrementally with values and conditions which are extracted from said directed-acyclic graph.
Claim 22
Dependent Claim
27 words
A method as recited in claim 19 further comprising the step of: processing said directed-acyclic graph using register transfer level nodes to extract said values and conditions.
Claim 23
Dependent Claim
29 words
A method as recited in claim 18 wherein initial state values are extracted from said directed-acyclic graph corresponding to said state register by a generic state value extraction algorithm.
Claim 24
Dependent Claim
84 words
A method as recited in claim 18 further comprising the step of: producing a plurality of state values and conditions from said directed-acyclic graph with a generic state value extraction algorithm; wherein extracting said register level state transition table includes using said generic state value extraction algorithm for explicit state value extraction from said directed-acyclic graph, and using said generic state value extraction algorithm for implicit state value extraction from said directed-acyclic graph evaluated when said state register is substituted by a state value.
Claim 25
Independent Claim
124 words
A system for fabricating an integrated circuit comprising: a digital computer system; a hardware description language input into a digital computer with a user input device, said hardware description language describing a state machine in terms of behavior; an extractor implemented on said computer to extract a register level state transition table from said hardware description language; a transition table generator implemented on said computer to generate a logic level state transition table; a synthesizer implemented on said computer to synthesize a state machine structural netlist from said logic level state transition table; and a combiner implemented on said computer system to combine on said computer said state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist.
Claim 26
Independent Claim
124 words
A system for fabricating an integrated circuit comprising: a digital computer system; a hardware description language input into a digital computer with a user input device, said hardware description language describing a state machine in terms of behavior; an extractor implemented on said computer to extract a register level state transition table from said hardware description language; a transition table generator implemented on said computer to generate a logic level state transition table; a synthesizer implemented on said computer to synthesize a state machine structural netlist from said logic level state transition table; and a combiner implemented on said computer system to combine on said computer said state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist.
Claim 27
Dependent Claim
27 words
A system as recited in claim 23 further comprising a chip compiler to convert said integrated circuit structural netlist into an IC layout including routing and placement.
Claim 28
Dependent Claim
23 words
A system as recited in claim 24 further comprising a mask layout generator to convert said IC layout into a multi-layer mask layout.
Claim 29
Dependent Claim
23 words
A system as recited in claim 25 further comprising a mask generator for making a plurality of masks from said multi-layer mask layout.
Claim 30
Dependent Claim
22 words
A system as recited in claim 26 further comprising semiconductor manufacturing equipment using said plurality of masks to produce an integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |